PTAB

IPR2014-01145

ATopTech Inc v. Synopsys Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Static Timing Analysis with Exceptions
  • Brief Description: The `’127` patent discloses methods for performing static timing analysis on electronic circuit designs. The technology involves propagating "timing tables" containing signal delay information through a circuit description and using associated "tags" with "labels" to track both clock information and user-defined, non-default timing constraints called "exceptions," such as false paths.

3. Grounds for Unpatentability

Ground 1: Claims 1-11 and 13 are Anticipated or Obvious over Belkhale

  • Prior Art Relied Upon: Belkhale ("Timing Analysis with known False Sub Graphs," a 1995 IEEE/ACM conference paper).
  • Core Argument for this Ground: Petitioner argued that the ’127 patent was allowed during prosecution based on the Examiner's mistaken belief that the claimed "exceptions" were not taught in the prior art. The petition asserted that Belkhale, a reference of record during the original prosecution, fully teaches the concept of exceptions by describing the identification and removal of "false paths" or "false sub graphs" during static timing analysis.
    • Prior Art Mapping: Petitioner contended that Belkhale discloses every limitation of independent claim 1. Belkhale's teaching of user-specified "false sub graphs" was mapped to the claimed step of "marking certain points... referenced by at least a first exception." The process in Belkhale of calculating and propagating "arrival times" (AT) through each node of a circuit graph was argued to meet the limitation of "propagating a plurality of timing tables." Finally, Belkhale’s use of a "set attribute," which is appended to the arrival time to track the specific false sub graphs a signal has passed through, was equated to the claimed "tag comprising at least a first label." Arguments for dependent claims asserted that Belkhale's "set attribute" for a false sub graph inherently represents a Boolean "OR" relationship among the points in that graph (claims 2-3, 10-11) and that Belkhale's method of discarding timing tables for satisfied false paths makes the claimed step of modifying a constraint value obvious (claims 5-6).
    • Key Aspects: This ground centered on re-interpreting a prior art reference that was before the original Examiner but allegedly not properly appreciated.

Ground 2: Claims 1-13 are obvious over Belkhale in view of Tom

  • Prior Art Relied Upon: Belkhale and Tom (Patent 5,210,700).
  • Core Argument for this Ground: This ground was presented as an alternative to Ground 1. Petitioner argued that to the extent Belkhale is found not to teach certain elements—specifically, a "tag" that also includes a clock identifier or a "timing table" comprising multiple delay values (e.g., rise and fall times)—Tom provides these missing features, and their combination would have been obvious to a person of ordinary skill in the art (POSITA).
    • Prior Art Mapping: Petitioner asserted that Belkhale teaches the core invention of tracking timing exceptions using tags ("set attributes"). Tom was presented as teaching the remaining elements, including the use of "clock tags" to associate clocking information with propagated delay values and the use of timing tables containing pairs of delay values (tph/tpl), which are analogous to the rise/fall times in the ’127 patent. The proposed combination results in a system that propagates multi-value timing tables with tags containing labels for both exceptions (from Belkhale) and clocks (from Tom), as claimed.
    • Motivation to Combine: A POSITA would combine the references to create a more accurate and comprehensive static timing analysis tool capable of handling multiple types of non-default timing alterations. The petition argued a POSITA seeking to apply Belkhale’s advanced false-path analysis to a circuit with multi-cycle clocks would be motivated to incorporate Tom’s clock-tracking tags. This would allow the system to correctly analyze timing for different clock domains while simultaneously eliminating logically impossible paths, leading to a more reliable design.
    • Expectation of Success: The combination was asserted to be straightforward because both references employ the same fundamental framework of propagating tagged delay values through a circuit graph. The ’127 patent specification itself was cited as evidence of this, as it first describes a system with only clock labels and then explains how to add exception labels, suggesting the integration is an obvious design choice.

4. Key Claim Construction Positions

  • "exception": Petitioner argued that a POSITA would understand an "exception" to be a "non-default timing constraint." This construction was crucial for mapping the term to the "false paths" and "false sub graphs" explicitly taught by Belkhale.
  • "tag": The petition argued that the claim phrase "a tag comprising at least a first label" requires only a single label indicating the marked point. It does not require an additional label identifying a clock. This construction supports the argument that Belkhale's "set attribute," which only identifies the false path, anticipates the "tag" limitation of claim 1.
  • "timing tables": Petitioner contended that this term is not limited to the preferred embodiment's four-value "RF timing table" but broadly covers the propagation of any delay value. This construction allows Belkhale's propagation of single "arrival time" (AT) values to satisfy the limitation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1-13 of Patent 6,237,127 as unpatentable.