ATopTech Inc v. Synopsys Inc

1. Case Identification

• Case #: IPR2014-01150
• Patent #: 6,567,967
• Filed: July 11, 2014
• Petitioner(s): ATopTech, Inc.
• Patent Owner(s): Synopsys, Inc.
• Challenged Claims: 1-4, 7-22, 32-36

2. Patent Overview

• Title: Method for Physical Design of Large Integrated Circuits
• Brief Description: The `’967` patent discloses a method for the physical design of large integrated circuits (ICs). The method involves logically partitioning a hierarchical design netlist into "atomic blocks," flattening the hierarchy above these blocks, and then grouping the atomic blocks into physical "place and route units" (PRUs) for independent layout and routing.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 and 7-22 are obvious over Fields in view of Su

• Prior Art Relied Upon: Fields (Carol Fields, Creating Hierarchy in HDL-Based High Density FGPA Design, Euro-DAC '95) and Su (Hsiao-Pin Su et al., Performance-Driven Soft-Macro Clustering and Placement by Preserving HDL Design Hierarchy, ISPD-98).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Fields, which teaches a methodology for physically implementing hierarchical circuit designs, disclosed most elements of independent claim 1. Specifically, Fields taught selecting "atomic blocks" (by re-grouping sub-hierarchical modules from a design), flattening the hierarchy (by eliminating original higher-level blocks in the re-grouping process), and partitioning these blocks into a plurality of regions corresponding to PRUs. Petitioner contended that Fields did not explicitly teach the final claimed step of positioning the atomic blocks within each PRU.
  • Petitioner asserted that Su supplied this missing element. Su taught a detailed methodology for placing components within a single PRU, including floorplanning for hard macros and then placing soft macros in the remaining rectilinear area. Petitioner argued that applying Su’s intra-PRU placement technique to each of the multiple PRUs generated by Fields' method rendered the claims obvious. Arguments for dependent claims followed this primary logic, with Su providing teachings for features like rectilinear soft block shapes and placement around hard blocks.
  • Motivation to Combine: A POSITA would combine Fields and Su because they addressed complementary aspects of the same problem in the electronic design automation (EDA) field. Fields provided a macro-level strategy for partitioning a large design into manageable PRUs, while Su provided a micro-level strategy for efficiently arranging components inside a single PRU. Combining Fields' partitioning with Su's placement was a logical and predictable step to create a complete and optimized physical design workflow.
  • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying known design principles to improve a known process, yielding predictable improvements in design efficiency and performance.

Ground 2: Claims 32-36 are anticipated by or obvious over Su

• Prior Art Relied Upon: Su.
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Su alone anticipated or rendered obvious independent claims 32 and 33, which recite a method of fitting an IC design into a predefined area. Petitioner contended that Su's disclosed methodology directly mapped to the claimed steps. Su's method began with a floorplanning procedure to determine the optimal placement of hard macros (the claimed "hard blocks") within a predefined area. Following this, Su's method explicitly extracted a "rectilinear area" from the space left unoccupied by the hard macros for the placement of soft macros (the claimed "soft blocks" and "hierarchical blocks").
  • Petitioner asserted this two-step process of placing hard blocks first and then fitting soft/hierarchical blocks with rectilinear shapes into the remaining space read directly on the limitations of claims 32 and 33. The dependent claims (34-36), which add limitations requiring the presence of multiple blocks, a soft block, and multiple hard blocks, were also allegedly disclosed in Su's figures and examples.

4. Key Claim Construction Positions

• Flattening (cl. 1): Petitioner proposed the construction "removing levels of hierarchy." It argued this term should not be limited to removing only the hierarchy above the selected atomic blocks, as such a reading would render other claim language redundant and superfluous.
• Partitioning (cls. 1, 4, 7, 13-14, 16-18): Petitioner proposed the construction "dividing up a logical representation of a circuit design into physically realizable sections... that can be grouped together to create an additional level of hierarchy." The core of this process was argued to be the grouping or clustering of atomic blocks into PRUs.
• Place and Route Unit (PRU) (cls. 1-4, 13-21): Petitioner proposed this term means "sections created to represent the physical partitioning of the IC design." It argued that a PRU is simply a section of the IC design and should not be limited by the specific manner of its creation.
• Dummy Block (cls. 10, 11): Petitioner proposed this term means "a block that is created as a container for standard cells." This block would not have existed in the original netlist but is created during import to group standard cells.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 7-22, and 32-36 as unpatentable.