PTAB

IPR2014-01371

Smart Modular Technologies Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Data Transfer Scheme for Non-Volatile Memory Module
  • Brief Description: The ’187 patent discloses hybrid memory systems that provide non-volatile backup for a volatile memory system. The invention relates to a method and system for transferring data from a volatile memory subsystem to a non-volatile one by first transferring portions of data words into a buffer and then transferring the entire data word from the buffer.

3. Grounds for Unpatentability

Ground 1: Anticipation by Fukuzo - Claims 1, 2, 6-11, 15-20, 24-27, 31, and 32 are anticipated under 35 U.S.C. §102 by Fukuzo.

  • Prior Art Relied Upon: Fukuzo (Application # 2006/0294295).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fukuzo discloses a memory chip device comprising a volatile SDRAM subsystem, a non-volatile flash memory subsystem, a controller, and a FIFO buffer. Petitioner asserted that Fukuzo teaches transferring 8-bit sequences of a 32-bit data word from SDRAM bank arrays (alleged to be the claimed "segments") into the FIFO buffer during backup operations. Subsequently, the entire 32-bit data word is transferred from the buffer to the flash memory, which Petitioner contended expressly or inherently discloses every limitation of the challenged independent claims. For dependent claims, Fukuzo’s disclosure of ECC logic between the buffer and flash memory was argued to teach the error correction limitations.

Ground 2: Anticipation by Miura - Claims 1-3, 6, 9-12, 15, 18-21, 24-28, 31, and 32 are anticipated under §102 by Miura.

  • Prior Art Relied Upon: Miura (Patent 6,952,368).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Miura discloses a complete memory system with volatile DRAM chips, a flash chip for backup, and a controller chip that includes a buffer. Miura’s system allegedly uses two distinct DRAM chips (DRAM 1 and DRAM 2) that constitute the claimed first and second "segments" of the volatile memory subsystem. Petitioner argued that Miura teaches transferring portions of a 16-bit data word from these DRAM segments into the controller’s buffer, and subsequently transferring the entire data word from the buffer to the flash memory, thereby anticipating the independent claims. Miura’s teaching of self-refresh for an inactive DRAM chip during access to the other was argued to anticipate dependent claims requiring inactivation.

Ground 3: Obviousness over Sanders and Freescale - Claims 1, 2, 6-11, 15-20, 24-27, 31, and 32 are obvious over Sanders in view of Freescale.

  • Prior Art Relied Upon: Sanders (’896Pub, Application # 2006/0069896) and Freescale (“MPC8560 PowerQUICC™ III Compact Flash Interface Design,” Dec. 2006).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Sanders discloses a portable device memory system with multiple volatile memory devices (e.g., 204-214) functioning as segments and a microcontroller with a RAM buffer. Freescale discloses a standard non-volatile flash memory module (a Compact Flashcard) for use in portable devices. Petitioner argued that the combination of Sanders’s volatile memory architecture with Freescale’s non-volatile storage module creates the memory system recited in the independent claims.
    • Motivation to Combine: A POSITA would combine Sanders’s memory system with Freescale’s standard flash memory module to achieve the well-known goal of providing non-volatile backup storage. Sanders explicitly describes its system interfacing with other devices, and Freescale provides a suitable, commercially standard flash memory solution for that purpose.
    • Expectation of Success: The combination involved integrating known components—a memory controller and a standard flash card—using well-understood interfaces. Therefore, a POSITA would have a high expectation of success in creating a functional hybrid memory system.

  • Additional Grounds: Petitioner asserted additional challenges including: obviousness of claims 3, 12, 21, and 28 over Fukuzo and Wong 2001; obviousness of claims 4, 5, 9, 13, 14, 18, 22, 23, 29, and 30 over Fukuzo and JEDEC 21-C; obviousness of claims 4, 5, 13, 14, 22, 23, 29, and 30 over Miura and JEDEC 21-C; anticipation of certain claims by Park ‘251; and obviousness of other claims over Park ‘251.

4. Key Claim Construction Positions

  • memory subsystem: Petitioner proposed construing this term as "two or more, memory components." This construction was argued to be critical for the invalidity arguments, as the prior art references (e.g., Fukuzo, Miura) disclose multiple memory chips or distinct bank arrays. Under this construction, these multiple components would qualify as the claimed "segments" within the volatile memory subsystem, thereby satisfying a key limitation of the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-32 of Patent 8,516,187 as unpatentable.