PTAB

IPR2014-01374

Smart Modular Technologies Inc v. Netlist Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Memory Board With Self-Testing Capability
  • Brief Description: The ’501 patent discloses a memory system, such as a memory module, with on-board Built-In Self-Test (BIST) capabilities. The alleged invention is a specific BIST configuration featuring a control circuit that generates address and control signals, and a plurality of independently operable data handlers that generate test data for writing to memory chips.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-2, 4-6, 9-11, 14-17, and 20 under 35 U.S.C. § 102 by Averbuj

  • Prior Art Relied Upon: Averbuj (Patent 7,392,442)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Averbuj discloses every element of the challenged claims. Averbuj teaches a BIST architecture for electronic devices, including circuit boards with memory. This architecture includes a "BIST controller 4" that functions as the claimed "control circuit" by generating address and control signals (SET ADDRESS and CMD_REQ signals). Averbuj also discloses pairs of "sequencers 8" and "memory interfaces 10" which collectively function as the claimed "plurality of data handlers." Petitioner contended these handlers operate independently, as each sequencer controls application speed for its corresponding memory component, and each memory interface includes a "data generation unit 44" to generate test data (RAM_DIN) for writing to memory components 12A-N. The system is configured to test the on-board memory using the signals and data generated by these components, thus anticipating independent claims 1 and 16 and their corresponding dependent claims.

Ground 2: Obviousness of Claims 1-6, 9-11, 14-17, and 20 over Rajan in view of Averbuj

  • Prior Art Relied Upon: Rajan (Patent 7,379,316), Averbuj (Patent 7,392,442)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Rajan provides the base memory system, disclosing a dual in-line memory module (FBDIMM) architecture with an Advanced Memory Buffer (AMB) chip and stacked memory chips, where each stack includes an interface chip for performing BIST. This FBDIMM module corresponds to the claimed "memory system," the AMB chip to the "control circuit," and the multiple interface chips to the "plurality of data handlers." Averbuj was argued to supply any missing details, such as its disclosure of a BIST architecture with independently operating sequencers (data handlers) and a dedicated data generation unit. The combination of Rajan's FBDIMM structure with Averbuj's specific BIST control and data handling functions rendered the claims obvious.
    • Motivation to Combine: A POSITA would combine these references because Averbuj teaches a versatile BIST architecture applicable to any electronic device with memory, including the FBDIMM module disclosed by Rajan. A POSITA would have been motivated to implement the known, robust BIST architecture from Averbuj into Rajan's memory module to provide or improve its self-testing capabilities, a predictable and desirable enhancement.
    • Expectation of Success: The combination involved applying a known testing architecture (Averbuj) to a known memory module type (Rajan), which would have been a straightforward integration for a POSITA with a reasonable expectation of success.

Ground 3: Obviousness of Claims 7-8, 12-13, and 18-19 over Averbuj in view of Best and Pandey

  • Prior Art Relied Upon: Averbuj (Patent 7,392,442), Best (Patent 8,233,303), and Pandey (Patent 6,934,205)

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds upon the BIST system of Averbuj, as supplemented by Best, to add the specific verification and data calculation features taught by Pandey. Dependent claim 7 requires verifying read data corresponds to written data "without storing a copy" of the written data. Petitioner argued that while Averbuj discloses comparing read data to expected data, Pandey explicitly teaches a comparator that generates the expected data signal at the time of comparison, obviating the need to store the original test data. This addresses the "without storing a copy" limitation. Similarly, Pandey's disclosure of calculating comparison data on-the-fly and comparing it to read data was used to meet the limitations of claims 8, 12, and 13.
    • Motivation to Combine: A POSITA, starting with the Averbuj/Best memory testing system, would have been motivated to incorporate Pandey's verification technique. Pandey's method of generating expected data during the read phase represents a known and more efficient alternative to storing and retrieving test patterns. A POSITA would combine these teachings to improve the BIST system's efficiency and reduce memory overhead, a common design goal.
    • Expectation of Success: Integrating a known comparator and verification logic (Pandey) into a standard BIST architecture (Averbuj/Best) was presented as a predictable modification that would have yielded the expected benefits of improved efficiency.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 3 is obvious over Averbuj and Best, and that claims 7-8, 12-13, and 18-19 are obvious over Rajan, Averbuj, and Pandey, relying on similar motivations and combinations of the core prior art references.

4. Key Claim Construction Positions

  • "operated independently": Petitioner proposed this term means "capable of operating in the absence of signals therebetween." This construction was central to arguing that Averbuj's sequencers, which control application speed for their respective memory components without communicating with each other, meet the claim limitation for independently operating data handlers.
  • "to generate": Petitioner proposed this term means "to cause or initiate transmission." This construction was used to argue that the data generation units in the prior art, which produce and provide test patterns, satisfy the claim requirement of data handlers "configured to generate data."

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-20 of the ’501 patent as unpatentable.