PTAB

IPR2014-01469

EMC Corp v. Acqis LLC

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1. Case Identification

2. Patent Overview

  • Title: Serial Peripheral Component Interconnect Bus
  • Brief Description: The ’814 patent describes a modular computer system where a portable "attached computer module" (ACM) connects to a "peripheral console." The core of the invention is a high-speed, serial interface, referred to as the XPBus, that uses low voltage differential signaling (LVDS) to communicate between the two components, effectively creating a serialized Peripheral Component Interconnect (PCI) bus interface.

3. Grounds for Unpatentability

Ground 1: Obviousness over Flint, Gulick, and Mathers - Claims 24, 31-33 are obvious over Flint in view of Gulick and Mathers.

  • Prior Art Relied Upon: Flint (Patent 5,608,608), Gulick (Patent 6,148,357), and Mathers (Patent 6,012,145).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Flint disclosed the foundational modular computer system, teaching a portable "cartridge" (the claimed ACM) that connects to a "chassis" (the claimed console) via a serial bus, which could be an IEEE 1394 serial bus. Flint's "local bus interface" serves as the claimed "north bridge" or "peripheral bridge," which is coupled to the processor without an intervening PCI bus and communicates serially with peripherals. However, Flint did not explicitly teach coupling main memory through this north bridge or specific security features. Gulick was introduced to supply the missing memory coupling, as it taught integrating a memory controller into the north bridge to improve performance and simplify design. Mathers was introduced to supply the claimed security features, as it taught a password-protection program stored in mass memory that executes upon power-up.
    • Motivation to Combine: A POSITA would combine Flint with Gulick to improve system performance, reduce component count, and simplify board layout by integrating the memory controller into the north bridge, which was a known design choice. A POSITA would have been motivated to add the password protection of Mathers to Flint’s system to provide a well-known method for controlling unauthorized access to data.

Ground 2: Obviousness over Horst and Mathers - Claims 24, 31-33 are obvious over Horst in view of Mathers.

  • Prior Art Relied Upon: Horst (TNet: A Reliable System Area Network, 15 IEEE Micro 37 (Feb. 1995)) and Mathers (’145 patent).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Horst, which described the TNet system area network architecture, taught the core technical concepts of the ’814 patent. Horst disclosed processor nodes (modules) connecting to a "system cabinet" (console) via point-to-point, low-voltage differential serial links (ECL, a precursor to LVDS). A custom ASIC in Horst served as the claimed north bridge, connecting directly to the processor's system bus without any intervening PCI bus and coupling the processor to main memory. This ASIC communicated serialized PCI-like transactions over the TNet links to peripherals. As in Ground 1, Mathers was cited to teach the claimed security and password-prompting functionalities.
    • Motivation to Combine: A POSITA reviewing Horst’s high-performance computing architecture would have been motivated to incorporate the conventional security features taught by Mathers. Adding password protection was a simple and predictable solution to the common problem of securing data on storage devices within such a system.

Ground 3: Obviousness over Bogaerts, Gulick, Mathers, and James - Claims 24, 31-33 are obvious over Bogaerts in view of Gulick, Mathers, and James.

  • Prior Art Relied Upon: Bogaerts (Application of the Scalable Coherent Interface to Data Acquisition at LHC (Oct. 1996)), Gulick (’357 patent), Mathers (’145 patent), and James (Patent 5,961,623).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Bogaerts described a multi-modular computing system using VME CPU modules connected via the IEEE 1596 SCI standard, a serial, LVDS protocol. This established the claimed modular system with a serial LVDS interconnect for communicating PCI transactions. However, the PCI-SCI adapter in Bogaerts was not directly coupled to the processor bus. Petitioner introduced James and Gulick to remedy this. James taught a system using SerialExpress (a hybrid of SCI and IEEE 1394) where a host adapter (north bridge) was coupled directly to the CPU without an intervening PCI bus. Gulick similarly taught replacing the parallel PCI bus with a serial bus directly coupled to the north bridge for increased speed. Mathers was again used to provide the password security limitations.
    • Motivation to Combine: A POSITA would combine these references to improve performance. Specifically, a POSITA would apply the teachings of James and Gulick to Bogaerts's SCI-based system to gain faster processor access by coupling the bridge/adapter directly to the CPU, removing the bottleneck of an intervening PCI bus. James provided a strong motivation, as it described SerialExpress as the next iteration of the SCI standard used by Bogaerts.

  • Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds 4-6) based on the same primary combinations as Grounds 1-3, but further in view of an LVDS Owner's Manual to provide additional support that LVDS channels with bidirectional capabilities were well-known and obvious to implement.

4. Key Claim Construction Positions

  • "PCI bus transaction": Petitioner proposed construing this term as "a data signal communication with an interconnected peripheral component," adopting a broad definition from a related district court litigation to argue that the prior art's general data communications met this limitation.
  • "Low Voltage Differential Signal": Petitioner proposed the construction "a differential signal using low voltage," arguing that the term was not limited to any specific LVDS standard and should be interpreted broadly based on the patent's specification.
  • "Serial Bit Channel": Petitioner proposed this term means "channels numbering fewer than the number of parallel lines in the PCI bus channels," arguing the key aspect was serialization relative to a parallel PCI bus, not a specific number of lines or transmission order.

5. Relief Requested

  • Petitioner requests institution of IPR and cancellation of claims 24, 31, 32, and 33 of the ’814 patent as unpatentable under 35 U.S.C. §103.