Qualcomm Technologies Inc v. Progressive Semiconductor Solutions LLC

1. Case Identification

• Case #: IPR2014-01504
• Patent #: 6,862,208
• Filed: September 15, 2014
• Petitioner(s): Qualcomm Technologies, Inc. and Qualcomm Incorporated
• Patent Owner(s): Progressive Semiconductor Solutions LLC
• Challenged Claims: 1, 2, 4, 7-9, 22, and 25

2. Patent Overview

• Title: Memory Device and Method Using a Self-Timed Latch
• Brief Description: The ’208 patent discloses memory devices, such as those used in integrated circuits, that feature a sense amplifier for amplifying a data signal, an isolation circuit for decoupling a memory cell from the sense amplifier, and a self-timed latch for storing the amplified data. The purported invention is the replacement of a conventional clocked latch with a self-timed one to improve speed and reduce power consumption.

3. Grounds for Unpatentability

Ground 1: Anticipation by Johnson - Claims 1, 2, 4, 7-9, 22, and 25 are anticipated by Johnson under pre-AIA 35 U.S.C. §102(b).

• Prior Art Relied Upon: Johnson (Patent 5,297,092).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Johnson, which was not considered during prosecution, expressly discloses a memory device with every element of the challenged claims. Johnson teaches a sense amplifier and a self-timed latch for sensing and latching data from bit lines. It also discloses an isolation circuit (transistors 62a, 62b) to decouple the bit lines from the sense amplifier during evaluation, which improves performance. For limitations that might not be explicit, Petitioner contended Johnson’s disclosure is inherent. For example, because Johnson’s sense amplifier evaluates logic levels on bit lines selected from multiple bit lines, and each bit line pair is coupled to a memory cell, the amplifier necessarily amplifies a data signal from a selected memory cell, thus meeting that limitation of claim 1. Similarly, Johnson’s disclosure of memory cells coupled to bit lines inherently includes coupling to word lines, as this was a necessary and fundamental aspect of memory array architecture at the time.

Ground 2: Obviousness over Johnson and Mizuno - Claims 1, 2, 4, 7-9, 22, and 25 are obvious over Johnson in view of Mizuno under pre-AIA 35 U.S.C. §103(a).

• Prior Art Relied Upon: Johnson (Patent 5,297,092) and Mizuno (Patent 5,943,284).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted this ground as an alternative to anticipation. Johnson provides the foundational memory circuit with a sense amplifier, isolation circuit, and a self-timed latch. If Johnson were found not to teach amplifying a data signal from a selected memory cell, Mizuno explicitly supplies this teaching. Mizuno discloses that when data is read, "the data of the memory cell, as connected to the selected word line, is sent through the bit line pair to the sense amplifier so that it is amplified."
  • Motivation to Combine: A POSITA would combine Mizuno’s teaching of selecting a specific memory cell for reading with Johnson’s memory architecture for a simple reason: it was well known and fundamental that to read a specific value from a memory array, the specific memory cell holding that value must be selected. Combining these known elements would have been a matter of applying a well-understood principle to achieve a predictable result.
  • Expectation of Success: A POSITA would have had a high expectation of success, as the combination merely applies a known selection technique (selecting a cell via a word line) to a known memory circuit to perform its basic function.

Ground 3: Obviousness over Johnson and Admitted Prior Art - Claims 22 and 25 are obvious over Johnson in view of the Admitted Prior Art under pre-AIA 35 U.S.C. §103(a).

• Prior Art Relied Upon: Johnson (Patent 5,297,092) and Admitted Prior Art from the ’208 patent specification.
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses the limitation in method claim 22 requiring "each of the plurality of memory cells coupled to a bit line and to a word line." Petitioner argued that while Johnson discloses memory cells coupled to bit lines, if this is deemed insufficient to teach coupling to a word line, the ’208 patent itself provides the missing element. The specification of the ’208 patent, in describing the background art (FIG. 1), explicitly states that memory cells in an array are "each coupled to a pair of differential bit lines ... [and] coupled to a word line." This statement constitutes an admission that this configuration was well known prior art.
  • Motivation to Combine: A POSITA would combine the admitted prior art’s teaching of word line coupling with Johnson’s circuit because coupling memory cells to both bit lines and word lines was the standard and necessary method for properly addressing and accessing individual memory cells within an array. It would have been obvious to apply this fundamental architecture to the memory cells in Johnson’s device.

4. Arguments Regarding Discretionary Denial

• Petitioner argued for institution by highlighting that its proposed rejections raise new issues that the Examiner did not previously consider during the prosecution of the ’208 patent. Specifically, the Johnson reference was never before the Patent Office. Petitioner contended that if the Examiner had been aware of Johnson, the challenged claims would not have issued.

5. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1, 2, 4, 7-9, 22, and 25 of the ’208 patent as unpatentable.