Xilinx Inc v. PLL Technologies Inc

1. Case Identification

• Case #: IPR2015-00148
• Patent #: 6,356,122
• Filed: October 24, 2014
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): PLL Technologies, Inc.
• Challenged Claims: 1-20

2. Patent Overview

• Title: Clock Synthesizer with Programmable Input-Output Phase Relationship
• Brief Description: The ’122 patent discloses a phase-locked loop (PLL) based clock circuit for clock synthesis and synchronization. The asserted novelty is the inclusion of a programmable delay circuit in both the reference signal path and the feedback signal path to allow for programmable control of the input-output phase relationship.

3. Grounds for Unpatentability

Ground 1: Anticipation over Nienaber - Claims 1, 7-10, and 14 are anticipated by Nienaber under 35 U.S.C. §102(b).

• Prior Art Relied Upon: Nienaber (Patent 4,611,230).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Nienaber, which discloses a phase-shifting circuit for a video centering control system, meets every limitation of the independent claims. Nienaber’s circuit includes a voltage-controlled oscillator (VCO), a reference path receiving a vertical sync signal (a type of clock signal), and a feedback path from the VCO output. Critically, Petitioner asserted that Nienaber discloses placing an “adjustable” delay circuit in both the reference path (delay circuit 12) and the feedback path (delay circuit 26). Under the broadest reasonable interpretation standard, Petitioner contended that Nienaber’s "adjustable" delay circuits are inherently "programmable" as required by the claims.
  • Key Aspects: This ground asserted that the core inventive concept—placing adjustable/programmable delays in both paths of a PLL—was fully disclosed in a single prior art reference that predated the ’122 patent by over a decade.

Ground 2: Obviousness over Nienaber and Young - Claims 1-3, 7-10, 14, and 17 are obvious over Nienaber in view of Young under 35 U.S.C. §103.

• Prior Art Relied Upon: Nienaber (Patent 4,611,230) and Young (Patent 5,446,867).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground was presented as an alternative to the anticipation argument. Petitioner argued that if Nienaber’s "adjustable" delay circuits were deemed not to meet the "programmable" limitation, Young explicitly taught this feature. Young discloses a PLL clock circuit with a delay line in the feedback path that is expressly described as being "programmed" using a control signal to add or subtract delay stages. Petitioner contended that Young's teachings on programming delay elements would supplement Nienaber's disclosure. For dependent claims, Young was also cited for its disclosure of a logic circuit to select a predetermined delay and a divider to create a divided output from the oscillator.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Nienaber and Young because both references disclose delay circuits within PLL clock circuits for the same purpose: adjusting the phase shift between a reference signal and a feedback signal. A POSITA would have found it obvious to modify the merely "adjustable" delay circuits of Nienaber to be explicitly "programmable" as taught by Young to achieve more precise and automated control.
  • Expectation of Success: The combination would have yielded the predictable result of a PLL circuit with programmable delay elements in both signal paths, as it involved applying a known programming technique (from Young) to a known PLL architecture (from Nienaber).

Ground 3: Anticipation over Chapman - Claims 8, 9, and 15 are anticipated by Chapman under 35 U.S.C. §102(a).

• Prior Art Relied Upon: Chapman (Patent 5,684,421).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner presented Chapman as an independent anticipatory reference for method claim 8. Chapman discloses a "timing signal generator" that delays a reference input (CLK) and a feedback input (TN) by a programmable amount of time to control the clock output. Specifically, Chapman’s Figure 1 shows an adjustable delay circuit (16) in the reference path and another adjustable delay circuit (18) in the feedback path. A delay controller (20) adjusts these delays based on user input, which Petitioner argued satisfies the "programming" step of dependent claim 9.
  • Key Aspects: This ground provided an alternative anticipation theory based on a delay-locked loop (DLL) circuit, arguing that Chapman’s DLL performed the same claimed method steps of generating a clock output by programmably delaying both reference and feedback inputs.

• Additional Grounds: Petitioner asserted numerous other obviousness grounds based on Nienaber and Chapman as primary references. These grounds added various secondary and tertiary references to teach limitations in dependent claims, including: Taketoshi (for multiple VCOs and a multiplexer); Kang (for selecting feedback path inputs); Sutardja (for reference and feedback counters); and Ferraiolo (for using a second PLL as an oscillator).

4. Key Claim Construction Positions

• "an oscillator, having a reference input receiving a reference signal, a feedback input receiving a feedback signal...": Petitioner argued that, for the purpose of the IPR, it would adopt the Patent Owner's interpretation from prosecution. This interpretation construes the claim to cover an oscillator (like a VCO) that has only a single physical input, where that input receives a combined signal generated from the separate reference and feedback signals (e.g., after they are compared by a phase detector). This construction was critical to mapping prior art where the VCO does not directly receive two separate signals.
• "a programmable delay circuit": Petitioner argued this term should be given its broadest reasonable interpretation to mean a delay circuit that can be programmed, configured, or adjusted to vary its delay time. This broad construction allowed Petitioner to argue that prior art describing delay circuits as "adjustable" met the claim limitation.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-20 of the ’122 patent as unpatentable.