PTAB

IPR2015-00175

ARM Inc v. Vantage Point Technology Inc

Key Events

Petition

petition

Title: Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having Multiple Instruction Pipelines and Separate TLBs for Each Pipeline
Brief Description: The ’750 patent describes a method for managing virtual memory in a data processing system that contains multiple, parallel instruction pipelines. The invention's stated purpose is to improve performance by providing a separate translation look-aside buffer (TLB) for each pipeline while using a common unit to handle translation updates when a TLB miss occurs.

Prior Art Relied Upon: Colwell (“A VLIW Architecture for a Trace Scheduling Compiler,” IEEE Transactions On Computers, Aug. 1988).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Colwell disclosed a Very Long Instruction Word (VLIW) processor with multiple parallel instruction pipelines (termed "integer processors" or "I boards"), each equipped with its own data TLB (DTLB). All pipelines received instructions from a common instruction issuing unit. Critically, Petitioner asserted that Colwell taught a common "trap handling code"—a software routine—that managed DTLB misses for all four pipelines. This shared trap code, which refills the TLBs from main memory, was identified as the claimed "direct address translation unit" that is shared by the different pipelines.
- Key Aspects: The argument centered on showing that a shared software-based mechanism (the trap code) for handling TLB misses satisfies the "direct address translation unit" limitation, anticipating all elements of independent claim 8 and its dependent claims.

Prior Art Relied Upon: Moore (“The PowerPC 601 Microprocessor,” IEEE Proc. Compcon, Feb. 1993).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Moore described the PowerPC 601 microprocessor, which contained multiple instruction pipelines (e.g., a branch processing unit and a fixed-point execution unit) that received instructions from a common dispatch unit. The system included separate translation buffers for each pipeline: a translation shadow array (TSA) for the instruction fetch pipeline and a main TLB within the Memory Management Unit (MMU) for the data access pipeline. Petitioner argued that the MMU and its associated hardware sequencer constituted a common "direct address translation unit" because this single hardware unit performed the page table walks to update both the TSA and the main TLB upon a translation miss.
- Key Aspects: This ground asserted that Moore’s hierarchical TLB structure, where the main MMU serves as a backup for the instruction-side TSA and handles all table walks, constituted a single, shared translation unit for separate pipelines. For dependent claims 9 and 10 ("whenever" clauses), Petitioner argued Moore taught that the main TLB is always updated if the TSA misses, satisfying the claim language.

Prior Art Relied Upon: Edenfield (“The 68040 Processor: Part 2, Memory Design and Chip Verification,” IEEE Micro, June 1990).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner advanced this ground based on the Patent Owner's alleged infringement theory, where separate instruction and data memory units within a single processor are considered distinct "instruction pipelines." Edenfield described the Motorola 68040 processor, which had separate memory management units (and associated Address Translation Caches, or ATCs) for instruction fetches and data accesses. Petitioner argued that Edenfield explicitly taught that a single Integer Unit (IU) executed a microcoded table walk algorithm to handle ATC misses for both the instruction and data sides. This common, microcode-executing IU was therefore the claimed shared "direct address translation unit."
- Key Aspects: The argument's strength relied on adopting the Patent Owner's own broad interpretation of "instruction pipeline" from related litigation to show that a well-known processor architecture anticipated the claims under that same interpretation.
Additional Grounds: Petitioner asserted additional challenges, including that claims 8-12 are anticipated by VAX 8800 (“Digital Technical Journal,” Feb. 1987) and rendered obvious by combinations including Colwell in view of Patent 4,933,835 and VAX 8800 in view of Patent 4,933,835.

"a first and a second instruction pipeline": Petitioner proposed this term be construed to mean at least two structures that each execute instructions received from a single, common instruction issuing unit. This construction was based on the only embodiment in the ’750 patent and was intended to limit the claim scope to super-scalar architectures, distinguishing it from multi-processor systems.
"whenever": For the dependent claims, Petitioner argued "whenever" should mean "every time that," implying a mandatory, simultaneous update of one translation buffer when another is updated. This contrasted with the Patent Owner's alleged litigation position that the term merely requires the ability for pipelines to access the same memory area.
"direct address translation unit": Petitioner proposed this term means "a common unit shared by all instruction execution pipelines that translates a virtual memory address." This construction emphasized the "common" and "shared" nature of the unit as a key limitation.

Petitioner argued that the Patent Owner took contradictory positions regarding the claim term "direct address translation unit" between a prior IPR (IPR2014-00467) and co-pending litigation. In the prior IPR, the Patent Owner allegedly argued that a multi-processor system like the VAX 8800 was deficient because it lacked a single, shared translation unit. However, in litigation, the Patent Owner allegedly accused multi-core processors where a "group of Memory Management Units" across separate cores constituted the single, shared unit. Petitioner asserted this inconsistency was a violation of the duty of candor and should preclude the Patent Owner from taking a narrow view before the Board while asserting a broad one in court.

Petitioner requests the institution of an inter partes review and the cancellation of claims 8-12 of the ’750 patent as unpatentable.