PTAB

IPR2015-00192

Apple Inc v. Vantage Point Technology Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Translating Virtual Addresses in a Data Processing System Having Multiple Instruction Pipelines and Separate TLB's for Each Pipeline
  • Brief Description: The ’750 patent describes a computing system architecture that uses multiple instruction pipelines, where each pipeline is provided with its own separate Translation Lookaside Buffer (TLB) to manage virtual-to-physical address translations. The invention is directed at managing address translation requests from these multiple pipelines to avoid the disadvantages of using a single shared memory array for this purpose.

3. Grounds for Unpatentability

Ground 1: Obviousness over PowerPC-1 and PowerPC-2 - Claims 1, 8, and 9 are obvious over PowerPC-1 in view of PowerPC-2.

  • Prior Art Relied Upon: PowerPC-1 (C.R. Moore, “The PowerPC 601 Microprocessor,” Compcon Spring ’93) and PowerPC-2 (M.S. Allen et al., “Multiprocessing Aspects of the PowerPC 601,” Compcon Spring ’93).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of PowerPC-1 and PowerPC-2, which describe different aspects of the same PowerPC 601 microprocessor, disclosed every element of the challenged claims. The PowerPC 601 architecture includes multiple instruction pipelines (a "Branch instruction pipeline" and a "Fixed Point pipeline"). It also has separate translation buffers for these pipelines: a translation shadow array (TSA) within the Instruction Fetch Unit (IFU) for the branch pipeline, and a 256-entry TLB within the Memory Management Unit (MMU) for the fixed-point (load/store) pipeline. Petitioner contended that the hashed page table structure described in the references, which is stored in memory and used to reload the TLBs after a miss, constituted the claimed "master translation memory." The hardware "Sequencer unit" in the PowerPC 601, which performs tablewalks through the page table upon a TLB miss, was identified as the claimed "direct address translation unit." Claim 9, which requires updating the second TLB "whenever" the first is updated, was allegedly met because the MMU TLB acts as a backup for the TSA, and a retrieved translation for a TSA miss is written to the MMU TLB as well.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine PowerPC-1 and PowerPC-2 because they describe different, complementary aspects of the same commercial product (the PowerPC 601 microprocessor). The references were published consecutively in the same conference digest and cross-reference each other, making their combination logical and necessary for a complete understanding of the processor's architecture.
    • Expectation of Success: A POSITA would have a high expectation of success in combining the teachings, as the references are not contradictory but rather provide distinct details about a single, integrated system.

Ground 2: Obviousness over PowerPC-1, PowerPC-2, and Denning - Claims 1, 8, and 9 are obvious over PowerPC-1 in view of PowerPC-2 and Denning.

  • Prior Art Relied Upon: PowerPC-1, PowerPC-2, and Denning (Peter J. Denning, “Virtual Memory,” Computing Surveys, Sept. 1970).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground reinforces Ground 1 and addresses a potentially narrower construction of "master translation memory" that requires it to be "main memory." Petitioner asserted that while the combination of PowerPC-1 and PowerPC-2 teaches a hashed page table that functions as the master translation memory, the Denning reference explicitly taught the well-known principle of storing page tables in a computer's main memory. Denning explained that storing page tables in main memory (a fast memory) is necessary to quickly access translation data during program execution, distinguishing it from slower auxiliary memory like disk drives.
    • Motivation to Combine: A POSITA, having combined PowerPC-1 and PowerPC-2 to understand the PowerPC 601 architecture, would be motivated to apply the fundamental virtual memory principles taught by Denning. Specifically, a POSITA would find it obvious to store the hashed page table of the PowerPC 601 in main memory to achieve the conventional and necessary performance benefits for virtual address translation, as taught by Denning.
    • Expectation of Success: The combination would be a straightforward application of a well-established design choice (storing page tables in main memory) to a known microprocessor architecture, leading to predictable performance improvements.

4. Key Claim Construction Positions

  • "a direct address translation unit" (claims 1, 8): Petitioner argued this term should be construed to require a single direct address translation unit that services virtual address translations from multiple pipelines. Petitioner asserted that this construction was consistent with a Board decision in a related IPR (IPR2014-00467) on the ’750 patent, which found that claim language and the specification overcame the general presumption that "a" means "one or more."
  • "master translation memory" (claims 1, 8, 9): Petitioner proposed that this term refers to a structure in memory that stores the comprehensive translation data used to populate the translation buffers (TLBs) when a TLB miss occurs. In the context of the prior art, this corresponds to the hashed page table structure of the PowerPC 601.
  • "activating...when..." (claims 1, 8): Petitioner argued that the term "when" should be construed broadly as "at a time that," indicating a temporal relationship between a TLB miss and the activation of the translation unit, without requiring immediate activation. This construction was supported by dictionary definitions and the patent's own disclosure of intermediate steps between a miss signal and the translation unit's operation.

7. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 8, and 9 of Patent 5,463,750 as unpatentable under 35 U.S.C. §103.