PTAB

IPR2015-00325

LG Electronics Inc v. ATI Technologies ULC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Graphics Processing System
  • Brief Description: The ’053 patent describes a multithreaded graphics processing system intended to improve processing efficiency and reduce delays. The disclosed system utilizes a memory device, described as a reservation station, to store multiple types of graphic command threads (e.g., pixel and vertex threads). An arbiter selects threads from the memory device based on a priority scheme and provides them to one or more command processing engines for execution.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lindholm and Admitted Prior Art - Claims 1, 2, and 5-7 are obvious over Lindholm in view of the Admitted Prior Art of the ’053 patent.

  • Prior Art Relied Upon: Lindholm (Patent 7,015,913) and the Admitted Prior Art of the ’053 patent.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lindholm’s multithreaded graphics processing system taught the core elements of the challenged claims. Specifically, Lindholm’s "Thread Control Buffer 420" was asserted to be the claimed memory device, and its "Instruction Scheduler 430" and "Instruction Dispatcher 440" were argued to collectively function as the claimed arbiter that selects threads based on priority. Lindholm’s "Execution Unit 470" was identified as the command processing engine. Petitioner contended that while Lindholm’s buffer stores both pixel and vertex thread state data, it does not explicitly disclose physically separate portions for each. To meet this limitation, Petitioner pointed to the Admitted Prior Art within the ’053 patent itself, which explicitly illustrates a system with separate buffers for different resource types (ALU resources vs. texture fetch resources). Petitioner further argued Lindholm’s Execution Unit inherently includes an arithmetic logic unit (claim 6) and a texture processing engine (claim 7) as it performs operations like coordinate transformation, shading, and blending.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Lindholm's advanced multithreaded processing architecture with the well-known partitioned storage approach described in the Admitted Prior Art. The motivation was to achieve the predictable benefits of faster and more convenient access to different data types, enhance the logical layout of the system, and further reduce processing stalls, all of which are consistent with the goals of Lindholm.
    • Expectation of Success: Combining a known memory organization technique with an existing processor architecture was a conventional design choice, presenting a straightforward implementation with a high expectation of success.

Ground 2: Obviousness over Moreton and Whittaker - Claims 1 and 2 are obvious over Moreton in view of Whittaker.

  • Prior Art Relied Upon: Moreton (Patent 7,233,335) and Whittaker (Patent 5,968,167).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Moreton discloses a multithreaded graphics system that meets most claim limitations. Moreton’s local memory, which allocates memory space based on thread type (e.g., pixel or vertex), corresponds to the claimed memory device with first and second portions. Moreton’s "memory controller 130" and "thread control buffer 127" were argued to function as the arbiter, and its plurality of "functional units (140-170)" were identified as the processing engine. However, Petitioner contended that Moreton does not explicitly teach selecting threads based on their relative priorities. To supply this missing element, Petitioner relied on Whittaker, which teaches a data processing management system that uses a "priority selection block 82" to select the thread with the highest priority for execution after a "resource checker 81" confirms availability.
    • Motivation to Combine: A POSITA would be motivated to modify Moreton's system by incorporating Whittaker's explicit priority selection mechanism. The stated motivation was to achieve more efficient data movement and to better and more flexibly balance processing loads among multiple instruction streams, thereby improving the overall throughput of the processing units. This was presented as a significant and common goal in the field of 3D graphics processing.
    • Expectation of Success: Integrating a known priority-based selection scheme into a multithreaded graphics processor was a well-understood design principle, and a POSITA would have had a high expectation of successfully implementing such a combination.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1, 2, and 5-7 are obvious over Stuttard (Patent 7,363,472) either alone or in combination with the Admitted Prior Art. Petitioner also argued claims 1 and 2 are obvious over Kimura (Patent 6,105,127) combined with the Admitted Prior Art. These grounds relied on similar theories that the primary references taught the core multithreaded processor architecture and that partitioning memory for different thread types was an obvious design choice. Petitioner also asserted that claims 5-7 are anticipated by Moreton and that claims 5-7 are obvious over the Admitted Prior Art alone.

4. Key Claim Construction Positions

  • Petitioner argued for broad constructions of key terms, consistent with their plain and ordinary meaning, to demonstrate that the prior art disclosures met the claim limitations.
    • "arbiter": Proposed construction was "any implementation of hardware and/or software that receives and provides a thread." This broad interpretation was critical to Petitioner's arguments that components like schedulers, dispatchers, and memory controllers in the prior art satisfied this limitation.
    • "command processing engine": Proposed construction was "any implementation of hardware and/or software that processes commands." This allowed Petitioner to map the term onto various components in the prior art, such as execution units or processing blocks, that perform computational tasks.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, and 5-7 of Patent 7,742,053 as unpatentable.