LG Electronics Inc v. Advanced Micro Devices Inc

1. Case Identification

• Case #: IPR2015-00328
• Patent #: 5,898,849
• Petitioner(s): LG Electronics, Inc.
• Patent Owner(s): Advanced Micro Devices, Inc.
• Challenged Claims: 1 and 14

2. Patent Overview

• Title: Microprocessor with Dedicated Caches for Executing Instructions in Parallel
• Brief Description: The ’849 patent describes a microprocessor architecture designed to improve performance by using multiple, parallel functional units (e.g., integer units, floating-point units). Each functional unit is coupled with its own dedicated local cache to reduce memory access delays and contention that would occur with a single, shared cache.

3. Grounds for Unpatentability

Ground 1: Anticipation over Crump - Claims 1 and 14 are unpatentable under 35 U.S.C §102(e) as anticipated by Crump.

• Prior Art Relied Upon: Crump (Patent 5,696,985).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Crump, which describes a parallel video processor, disclosed every element of the challenged claims. Crump's processor contains a plurality of programmable "microcoded engines" on a single chip, which Petitioner asserted are equivalent to the claimed "functional units." Each of Crump's engines is connected to its own dedicated instruction cache (I-cache) and data cache (D-cache), satisfying the local cache limitations. Petitioner contended that a "load store unit" within each microcoded engine performs the claimed function of generating a memory address from an address operand to retrieve a memory operand from the local D-cache. For claim 14, Petitioner argued that Crump's processors were explicitly designed to process video and graphic algorithms (e.g., MPEG2), thereby qualifying as a "multimedia unit" executing "multimedia instructions."

Ground 2: Anticipation over Boleyn - Claim 1 is unpatentable under 35 U.S.C §102(b) as anticipated by Boleyn.

• Prior Art Relied Upon: Boleyn ("A Split Data Cache for Superscalar Processors," ICCD '93).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Boleyn, a paper analyzing performance benefits of split data cache designs, anticipated claim 1. Boleyn explicitly discloses a superscalar processor with two main operational units: an "Integer Unit" and a "Floating Point Unit," which are the same exemplary functional units described in the ’849 patent. Boleyn teaches coupling these units to separate, dedicated data caches—an "Integer Data Cache" (dcache) and a "Floating Point Data Cache" (fcache)—to allow parallel memory access. Petitioner argued that Boleyn's disclosure of a "load unit" within the integer unit and a "float load unit" within the floating-point unit meets the claim limitation of a functional unit configured to generate a memory address from an operand to retrieve data from its respective local cache.

Ground 3: Obviousness over Yung in view of Boleyn - Claim 1 is obvious over Yung in view of Boleyn under 35 U.S.C §103(a).

• Prior Art Relied Upon: Yung (Patent 5,592,679) and Boleyn (ICCD '93).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner argued that Yung discloses a multi-level scheduling system with multiple "execution pipes," each containing "execution units" (the claimed functional units). To speed up operation, Yung teaches that each execution pipe includes a "local register buffer" to store operand values. While Yung does not explicitly disclose local caches, Petitioner contended that a person of ordinary skill in the art (POSITA) would have understood that a cache and a register buffer are both forms of localized storage. Petitioner argued that Boleyn explicitly teaches using dedicated local caches for functional units to improve performance. The missing claim elements in Yung—specifically, dedicated local caches and the mechanism for generating a memory address to retrieve operands from them—are supplied by Boleyn's load/store units and split data cache architecture.
  • Motivation to Combine: A POSITA would combine Yung and Boleyn to improve the performance of Yung's architecture. Yung does not clearly describe how data is retrieved from its register buffers. A POSITA seeking to implement or improve Yung's system would have been motivated to look to conventional solutions like those in Boleyn, which teaches a well-understood method of using load units to retrieve data from local caches, a known and more efficient form of local storage.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in replacing Yung's local register buffers with Boleyn's local caches, as this would involve applying a known technique (dedicated caches) to a known system (parallel processor architecture) to achieve a predictable result (improved performance and reduced memory access contention).

• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) alleging claims 1 and 14 are obvious over Araki (a 1994 IEEE article on a video DSP) in view of Boleyn.

4. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1 and 14 of the ’849 patent as unpatentable.