PTAB

IPR2015-00329

LG Electronics Inc v. Advanced Micro Devices Inc

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1. Case Identification

2. Patent Overview

  • Title: Universal Serial Bus Device or Host with DMA Mode
  • Brief Description: The ’715 patent discloses a universal serial bus (USB) device or host that combines a USB controller with a direct memory access (DMA) controller. The invention purports to improve data transfer efficiency, particularly for back-to-back USB packets, by using DMA channels to manage data flow between USB endpoints and memory without involving the main microprocessor.

3. Grounds for Unpatentability

Ground 1: Obviousness over USBN9602 and Intel 8237 - Claims 1, 10, and 25 are obvious over USBN9602 in view of Intel 8237.

  • Prior Art Relied Upon: USBN9602 (a National Semiconductor technical specification for a USB function controller) and Intel 8237 (an Intel datasheet for a high-performance programmable DMA controller).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that USBN9602, a USB controller, explicitly discloses support for DMA transfers using an external DMA controller to and from its endpoints. Intel 8237 is a well-known, industry-standard external DMA controller with four independent channels, satisfying the claimed "plurality of DMA channels." USBN9602 further discloses a DMA Control Register with a "DMA Source" field that selects one of its multiple endpoints for DMA transfer, thereby teaching a USB controller with multiple endpoints, each selectively programmed for a DMA channel. For dependent claim 10, Petitioner contended that a person of ordinary skill in the art (POSITA) would find it obvious to modify the unused bits in the Mask Register of the Intel 8237 DMA controller to incorporate the endpoint selection functionality from USBN9602's control register.
    • Motivation to Combine: A POSITA would combine the USBN9602 USB controller with a standard DMA controller like Intel 8237 for its intended and disclosed purpose: to offload data transfer tasks from the device's main microprocessor. This combination would predictably result in a more efficient and faster device, providing a clear motivation. The selection of Intel 8237 was argued to be obvious due to its ubiquity as a well-known DMA controller at the time.
    • Expectation of Success: The combination involved connecting standard, compatible interfaces (e.g., DREQ and DACK pins), a routine task for a POSITA with a high expectation of success.

Ground 2: Obviousness over EIFUFAL501 and Intel 8237 - Claims 1, 10, and 25 are obvious over EIFUFAL501 in view of Intel 8237.

  • Prior Art Relied Upon: EIFUFAL501 (a Seiko Epson user's manual for a USB Function Controller) and Intel 8237 (the same Intel DMA controller datasheet).
  • Core Argument for this Ground:
    • Prior Art Mapping: EIFUFAL501 describes a USB Function Controller (USBFC) that can be used with an optional external DMA controller for data transfers. Combining this with the multi-channel Intel 8237 controller would result in the claimed system. EIFUFAL501 discloses five endpoints and a DMA Control Register containing a "DMA Direction" bit that determines data flow, effectively selecting an endpoint for the DMA channel depending on the transfer direction (host-to-device or device-to-host). This combination teaches a USB controller with multiple endpoints selectively programmed for DMA. As in Ground 1, Petitioner argued it would be obvious to integrate the control functions from EIFUFAL501's register into the unused bits of Intel 8237's Mask Register to satisfy claim 10.
    • Motivation to Combine: The motivation was explicitly provided by EIFUFAL501, which states a DMA controller may be used to transfer data to and from the USBFC. A POSITA would be motivated to implement this optional DMA functionality to increase processing speed by relieving the main processor of memory transfer tasks. The choice of the widely-used Intel 8237 was a predictable design choice.
    • Expectation of Success: The EIFUFAL501 manual provides a block diagram showing how its USBFC connects to an optional DMA controller via a common data bus, making the integration straightforward and predictable for a POSITA.

Ground 3: Obviousness over USB97C100 and Dunnihoo - Claims 1, 10, 13, 22, 24, and 25 are obvious over USB97C100 in view of Dunnihoo.

  • Prior Art Relied Upon: USB97C100 (a Standard Microsystems technical specification for a USB peripheral controller) and Dunnihoo (Patent 6,185,641).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that USB97C100 is the commercial implementation of the Dunnihoo patent, given their nearly identical architectures (SIE, MMU, RAM, 8237 DMA controller, 8051 microcontroller) and stated purpose. Dunnihoo discloses a single data path between its Serial Interface Engine (SIE) and RAM, which functions as a DMA channel. Petitioner argued a POSITA would find it obvious to create separate receive and transmit DMA paths to increase efficiency, thereby creating a "plurality of DMA channels." For claims requiring endpoint selection (10 and 22), USB97C100 discloses a "Transmit FIFO Select Register" which is programmed with the number of a polled endpoint, thereby selecting that endpoint as the source of data to be retrieved from RAM and sent to the host.
    • Motivation to Combine: A POSITA would look to the Dunnihoo patent to understand the detailed operation of the highly similar USB97C100 controller. The motivation to modify Dunnihoo's single DMA path into separate transmit and receive paths was based on the simple and predictable engineering goal of improving system efficiency and throughput by eliminating data path contention.
    • Expectation of Success: The detailed disclosures and extreme similarity between the references would have provided a POSITA with a clear and reliable guide for implementing the claimed features.

4. Key Claim Construction Positions

  • "DMA mode": Petitioner proposed this term be construed as the "mode where a DMA channel is used as part of the process of transferring USB packets between a USB host and a USB device." This construction was argued to be consistent with the specification’s description that in a DMA mode, endpoints are programmed for DMA transmit or receive channels.
  • "DMA channel": Petitioner proposed this term be construed as "a path for moving data directly to or from memory locations without processor intervention." This broad construction was asserted as the broadest reasonable interpretation consistent with the patent and the general understanding of DMA technology.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 10, 13, 22, 24, and 25 of the ’715 patent as unpatentable.