PTAB

IPR2015-00330

LG Electronics Inc v. ATI Technologies ULC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Unified Shader Graphics Processing Architecture
  • Brief Description: The ’369 patent describes a graphics processing architecture that uses a single, unified shader to perform both vertex and pixel operations, rather than using separate, dedicated shaders for each function. The architecture includes an arbiter circuit that selects between different input types (e.g., vertex or pixel data) to be processed by the unified shader.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 are obvious over Lindholm in view of OpenGL

  • Prior Art Relied Upon: Lindholm (Patent 7,015,913) and OpenGL (OpenGL Graphics System: A Specification, Version 1.4).
  • Core Argument:
    • Prior Art Mapping: Petitioner argued that Lindholm discloses a graphics processor with a multithreaded processing pipeline (Execution Pipeline 240) that functions as a unified "shader" by performing both vertex and pixel operations. The system's Thread Control Buffer 420, which selects samples from either a Vertex Input Buffer or a Pixel Input Buffer for processing, was asserted to be the claimed "arbiter circuit." Petitioner mapped Lindholm’s Vertex Output Buffer 260 to the "vertex storage block" limitation. Petitioner contended that while Lindholm teaches the core unified architecture, it is silent on the specific cache structure of claim 1.f, which requires the vertex storage block to include a separate parameter cache and position cache. OpenGL was cited to supply this teaching, as its vertex processing diagrams show that transformed vertex information includes both position data ("Transformed Coordinates") and appearance attribute data ("Associated Data"), which are handled separately before rasterization.
    • Motivation to Combine: Petitioner asserted that a person of ordinary skill in the art (POSITA) would combine Lindholm with the teachings of the OpenGL specification to supply the missing cache structure. The motivation stemmed from the shared field of 3D graphics, the status of OpenGL as a widely-used industry standard, and the goal of improving performance. Modifying Lindholm's buffer to include separate parameter and position caches as taught by OpenGL would be an obvious design choice to allow for faster access and more efficient processing of vertex data.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining a known processor architecture with a standard API's data management techniques to improve performance is a predictable and well-understood engineering approach.

Ground 2: Claims 1-2 are obvious over Rich in view of OpenGL

  • Prior Art Relied Upon: Rich (Patent 5,808,690) and OpenGL (OpenGL Graphics System: A Specification, Version 1.4).
  • Core Argument:
    • Prior Art Mapping: Petitioner contended that Rich discloses an image generation system based on a Single Instruction, Multiple Data (SIMD) array of processing elements that perform both geometric processing (vertex operations) and shading/texturing (pixel operations), thereby functioning as a unified "shader." The Central Control Unit (CCU), which manages data flow and arbitrates requests between resources, was identified as the claimed "arbiter circuit." While Rich's system processes both vertex and pixel data, Petitioner argued it does not explicitly disclose a vertex storage block with distinct parameter and position caches (limitations 1.e and 1.f). OpenGL was again relied upon to teach this specific data organization and caching structure.
    • Motivation to Combine: Petitioner argued a POSITA would be motivated to modify Rich’s architecture by incorporating the caching techniques from the OpenGL standard to improve rendering efficiency, a common goal in 3D graphics. This motivation was strengthened by Rich's own disclosure that the use of external memory may be necessary due to the limited on-chip memory of its processing elements. This would lead a POSITA to consult industry standards like OpenGL for well-established methods of efficiently organizing and caching vertex data (both position and parameters) in external memory before rasterization.
    • Expectation of Success: Success would be expected, as implementing a well-known caching scheme from a graphics standard like OpenGL into a graphics processor like Rich's to improve data access speed is a conventional and predictable design modification.

Ground 3: Claims 1-2 are obvious over Stuttard in view of OpenGL

  • Prior Art Relied Upon: Stuttard (Patent 7,363,472) and OpenGL (OpenGL Graphics System: A Specification, Version 1.4).
  • Core Argument:
    • Prior Art Mapping: Petitioner asserted that Stuttard describes a graphics system where a processing core processes both vertex and pixel data, corresponding to the unified "shader." The system's thread manager, which provides instructions to control the processing blocks and data transfer, was argued to function as the "arbiter circuit." Petitioner mapped the local memory used for storing transformed vertex data in Stuttard to the "vertex storage block" limitation. Petitioner argued Stuttard itself suggests using caches to improve performance (e.g., a data cache in its binning unit to reduce stall time), but does not explicitly disclose the claimed storage block with separate parameter and position caches. This limitation was supplied by the OpenGL specification.
    • Motivation to Combine: The motivation to combine Stuttard and OpenGL was argued to be the desire for faster graphics processing. Because Stuttard already discloses using a data cache in its binning unit to reduce stall time, a POSITA would already be focused on caching as a performance-enhancement strategy. It would therefore be obvious to apply this same principle to the vertex data storage by implementing the specific, efficient parameter and position cache structure taught by the widely-adopted OpenGL standard.
    • Expectation of Success: A POSITA would have reasonably expected success in this combination, as it involved applying a standard, well-documented data caching and organization methodology (from OpenGL) to a known graphics processing architecture (Stuttard) to achieve a predictable performance improvement.

4. Key Claim Construction Positions

  • Petitioner argued that the term “means for performing vertex operations and pixel operations” in claim 1 is a means-plus-function limitation.
    • The claimed function was identified as "performing vertex operations and pixel operations."
    • The corresponding structure disclosed in the ’369 patent specification was identified as the "unified shader's processor 96" and its equivalents. This construction is central to Petitioner's mapping of the prior art shaders (e.g., Lindholm's Execution Pipeline, Rich's processing elements) to this limitation.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1 and 2 of Patent 7,327,369 as unpatentable under 35 U.S.C. §103.