PTAB

IPR2015-00460

Samsung Electronics Co Ltd v. Home Semiconductor Corp

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: METHOD FOR FORMING SELF-ALIGNED CONTACT HOLE
  • Brief Description: The ’997 patent discloses a method for fabricating self-aligned contact holes in semiconductor devices. The purported novelty is a streamlined process that combines the spacer formation and contact hole exposure steps into a single anisotropic etch, intended to reduce manufacturing steps and costs.

3. Grounds for Unpatentability

Ground 1: Anticipation over Doshi - Claims 1-14 are anticipated by Doshi under 35 U.S.C. §102.

  • Prior Art Relied Upon: Doshi (Patent 6,277,720).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Doshi discloses every limitation of claims 1-14. Doshi teaches a method of fabricating contact openings using a two-step etch process. First, a BPSG insulating layer is selectively etched, stopping on an underlying silicon nitride barrier layer. Second, a brief, "highly anisotropic" nitride etch clears the barrier layer from the contact opening, thereby exposing the diffusion region. Petitioner asserted that this second anisotropic etch simultaneously forms a spacer from the remaining silicon nitride on the sidewall of the gate electrode. This process directly maps to the key limitation of claim 1, which was the feature that applicant relied upon to overcome prior art during prosecution of the ’997 patent.
    • Key Aspects: Petitioner contended that Doshi, which was not considered during the original prosecution, explicitly teaches the very feature—simultaneous spacer formation and diffusion region exposure via a single anisotropic etch—that led to the allowance of the ’997 patent claims.

Ground 2: Anticipation over Becker - Claims 1 and 3-8 are anticipated by Becker under §102.

  • Prior Art Relied Upon: Becker (Patent 5,770,498).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Becker, like Doshi, teaches a method that anticipates the challenged claims. Becker’s process involves forming a conformal silicon nitride "spacer insulating layer" over a gate electrode and diffusion regions, followed by depositing a BPSG insulating layer. A two-step etch process then forms the contact opening. The first etch removes the BPSG layer selective to the nitride, and the second is an anisotropic etch of the nitride layer. This second etch exposes the underlying source/drain regions and simultaneously "produces the same spacer 34 profile as conventional processes" on the sidewalls of the gate electrode. Petitioner asserted this process discloses all limitations of independent claim 1 and dependent claims 3-8.

Ground 3: Obviousness over Becker in view of Wong - Claims 2 and 9-14 are obvious over Becker in view of Wong under §103.

  • Prior Art Relied Upon: Becker (Patent 5,770,498) and Wong ("Process Induced Degradation of Thin Oxides," 1987).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that while Becker teaches the core process, it does not expressly disclose the limitation of claim 2: "forming an oxide layer over the diffusion region and on the sidewalls of the gate electrode by thermal oxidation prior to forming the barrier layer." Becker discloses forming a gate electrode, which includes a polysilicon layer, by using conventional etching methods like reactive ion etch (RIE). Wong teaches that RIE processes used to define polysilicon gates can create defects in the thin gate oxide, degrading device yield. Wong further teaches that performing a reoxidation of the polysilicon sidewalls after the RIE step reduces these defects and improves yield significantly.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to apply Wong's yield-improving reoxidation technique to Becker's process. This would be done after etching the gate electrode (as in Becker) but before depositing the silicon nitride barrier layer. This thermal oxidation step would naturally form an oxide layer on the exposed polysilicon gate sidewalls and on the uncovered silicon of the diffusion regions, thus arriving at the invention of claim 2.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining these teachings, as applying a known yield-enhancement step (Wong) to a standard fabrication process (Becker) was a predictable and well-understood modification in the field.

4. Key Claim Construction Positions

Petitioner proposed constructions for several key terms under the broadest reasonable interpretation standard, arguing they were critical to mapping the prior art.

  • "forming a conformal layer of [etch barrier material] overlying the substrate" (claims 1, 9): Petitioner argued this term does not require the layer to be in direct contact with the substrate. Citing the ’997 patent’s specification, Petitioner contended that "overlying" means the layer is supported by the substrate, even with intermediate structures (like oxide layers and gate electrodes) in between.
  • "forming an oxide layer over the diffusion region" (claims 2, 9): Consistent with the above, Petitioner argued "over" means "above," not necessarily in direct contact. This construction allows an oxide layer formed on top of a diffusion region, even with an intervening gate oxide layer, to meet the claim limitation.
  • "spacer" (claims 1, 9): Petitioner proposed this term encompasses "a structure that spaces between two conductive structures," such as a gate electrode and a conductive plug, to prevent shorting, consistent with its functional description in the ’997 patent.
  • "etching an opening through the insulating layer self-aligned and borderless to the diffusion region" (claims 1, 9): Petitioner argued this describes using a single mask to etch through multiple layers, where the mask opening can be oversized relative to the underlying contact area, eliminating the need for precise alignment borders.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1-14 of the ’997 patent as unpatentable.