PTAB

IPR2015-00929

Apple Inc v. ZiiLabs Inc

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Petition
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1. Case Identification

2. Patent Overview

  • Title: Graphic Memory Management With Invisible Hardware-Managed Page Faulting
  • Brief Description: The ’425 patent relates to computer graphics rendering systems where a graphics accelerator unit manages the page faulting of texture data from memory. This process is performed "invisibly," or without the intervention of the host processor, to improve performance.

3. Grounds for Unpatentability

Ground 1: Obviousness over Herrell and Priem - Claims 1, 2, 6, and 11 are obvious over Herrell in view of Priem.

  • Prior Art Relied Upon: Herrell (Patent 5,301,287) and Priem (Patent 7,136,068).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Herrell and Priem disclose complementary aspects of a computer graphics system that a person of ordinary skill in the art (POSITA) would have combined. Herrell taught a system with a host CPU, main memory, and a virtual direct memory access (VDMA) interface that allows a graphics subsystem to directly access the host's virtual memory without involving the host CPU for most transfers. However, Herrell provided only a high-level description of the graphics subsystem itself. Priem, conversely, taught a detailed graphics accelerator with its own local ("dedicated") memory, texture engine, and a direct memory access (DMA) engine for managing texture data from system memory.

    • Petitioner contended that substituting Priem’s detailed graphics accelerator for Herrell’s generic subsystem would result in the claimed invention. In the combined system, the integrated VDMA of Herrell and DMA of Priem would function as a memory management unit on the graphics accelerator. This unit would manage page faulting of texture data from the host's main memory (per Herrell) to the accelerator's local, dedicated graphics memory (per Priem). This process would be "invisible" to the host processor, as Herrell explicitly taught that its VDMA allows data transfer "without the necessity of executing instructions in the host processor."

    • For claim 2, which recites an exception for when the accelerator "calls for data which has not recently been present in said main memory," Petitioner mapped this to Herrell's disclosure. Herrell taught that if a requested page is not in main memory and resides on the swap disk (bulk storage), the VDMA suspends activity and interrupts the host CPU to handle the page swap. This host intervention aligns directly with the claim's "except when" limitation.

    • For system claims 6 and 11, Petitioner argued Herrell supplied the CPU, main memory, and the "first memory management logic" (the host kernel managing virtual memory with a swap disk). Priem supplied the "graphics accelerator unit" with its rendering logic and dedicated memory. The "second memory management unit" that performs page faulting invisibly was the combination of Herrell's VDMA and Priem's DMA engine.

    • Motivation to Combine (for §103 grounds): Petitioner argued a POSITA would combine the references to improve the known system of Herrell with the more advanced graphics and texture processing capabilities disclosed by Priem. Herrell provided a robust interface to host memory, while Priem provided a specialized graphics processor. Integrating them was a predictable path to accelerate 3D graphics processing, enhance imagery, and improve the overall user experience by leveraging the strengths of each system.

    • Expectation of Success (for §103 grounds): Petitioner asserted that a POSITA would have had a high expectation of success, as combining the systems was a routine engineering task. The references were not technically incompatible and addressed complementary, well-understood components of computer graphics architecture.

4. Key Claim Construction Positions

  • "manages page faulting of texture data [...] invisibly to the host processor" (claims 1, 2): Petitioner argued this term should be construed to mean "when the page is not present, the graphics accelerator unit, rather than the CPU, automatically fetches the page of texture data from main memory and updates a page table." This construction was central to the argument that the invention's key feature—offloading memory management from the CPU—was taught by the combination of Herrell's VDMA and Priem's accelerator.
  • "dedicated graphics memory" (claims 2, 6, 11): Petitioner proposed this term means the "primary memory of the graphics accelerator unit for storing graphics data." This construction equates the claim term with on-card or local memory located on the graphics accelerator itself, as described in Priem, distinguishing it from the host system's main memory.
  • "normal texture memory" (claim 11): Petitioner argued that based on claim drafting principles (antecedent basis), this term should be construed as referring to the previously recited "dedicated graphics memory" within claim 11.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 2, 6, and 11 of the ’425 patent as unpatentable.