PTAB

IPR2015-01020

SanDisk Corporation v. NETLIST, INC.

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1. Case Identification

2. Patent Overview

  • Title: Memory Module with Command Signal Logic
  • Brief Description: The ’150 patent relates to memory modules for computer systems. The technology involves using a circuit on the memory module to allow it to operate with a greater number of lower-density memory devices than the computer system’s memory controller is designed to support, effectively simulating a module with fewer, higher-density devices.

3. Grounds for Unpatentability

Ground 1: Obviousness over Takeda and JEDEC - Claims 15, 16, 31, and 32 are obvious over Takeda in view of JEDEC.

  • Prior Art Relied Upon: Takeda (Japanese Patent Application Publication No. H10-320770) and JEDEC (JEDEC Standard 21-C: DDR SDRAM Registered DIMM Design Specification, Jan. 2002).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Takeda discloses the core concept of the ’150 patent: a memory module with more memory ranks than expected by the computer system. Takeda’s on-module bank control unit (a logic element) receives a first number of chip-select signals from the controller and generates a second, larger number of chip-select signals to control the additional physical ranks. This emulates a system with fewer, higher-density memory devices using more, lower-density devices. However, Takeda does not explicitly show standard components like a register or a phase-lock loop (PLL). Petitioner argued that JEDEC, a well-known industry standard for DDR memory modules, explicitly discloses the use of registers and PLLs on a DIMM to interface between a memory controller and DDR SDRAM devices. JEDEC shows the standard configuration of data lines, strobes, and command/address signals for such modules.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA), seeking to implement Takeda’s rank-multiplication concept in a modern DDR system, would have naturally consulted the JEDEC standard. Takeda itself acknowledged that memory module configurations are disclosed in JEDEC documents. A POSITA would combine Takeda's logic for emulating memory ranks with the standard DDR module components disclosed in JEDEC to achieve the predictable result of a functional, high-capacity DDR module with reduced cost and power consumption, as taught by Takeda.
    • Expectation of Success: Combining Takeda's rank-emulation logic with the standard JEDEC-compliant module architecture was argued to be a straightforward application of known design principles, leading to a high expectation of success.

Ground 2: Obviousness over Takeda, JEDEC, and Connolly - Claims 17, 22, 24, 26, and 33 are obvious over the combination of Takeda and JEDEC, further in view of Connolly.

  • Prior Art Relied Upon: Takeda (Japanese Patent Application Publication No. H10-320770), JEDEC (JEDEC Standard 21-C), and Connolly (Patent 6,070,217).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon Ground 1 by adding Connolly to teach limitations not explicitly disclosed by Takeda or JEDEC, specifically the use of "one or more switches" and "selectively isolating" memory device loads from the computer system. Petitioner argued that Connolly directly addresses the problem of reducing capacitive bus loading on high-density memory modules by placing bus switches between the module tabs and the RAM devices. These switches selectively isolate unselected memory banks from the data bus. This corresponds to the "selectively isolating one or more loads" limitation in independent claim 22 and the "switches" limitation in dependent claims 17 and 33.
    • Motivation to Combine: A POSITA designing a high-capacity module based on Takeda and JEDEC would be concerned with the increased electrical load from the additional memory devices. Connolly provides a known solution to this exact problem. A POSITA would combine Connolly's load isolation technique with the Takeda/JEDEC architecture to predictably improve the module’s electrical characteristics and reduce power consumption, a benefit explicitly mentioned in Connolly.
    • Expectation of Success: The integration of standard bus switches as taught by Connolly into a JEDEC-compliant memory module architecture was presented as a well-understood design choice with predictable, beneficial outcomes.

Ground 3: Anticipation by Amidi - Claims 15 and 31 are anticipated by Amidi.

  • Prior Art Relied Upon: Amidi (Application # 2006/0117152).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Amidi discloses every element of independent claims 15 and 31. Amidi describes a "transparent four rank DDR module" that emulates a two-rank module to the computer system. The module includes all claimed components: DDR memory devices arranged in ranks, a logic element (a CPLD), a register, and a PLL, all mounted on the module. Amidi's circuit receives a set of input signals (including two chip-select signals) from the computer system and translates them for the physical memory, which has more ranks and requires more chip-select signals (four). This explicitly teaches translating between a system memory domain (expecting higher-density memory) and a physical memory domain (using lower-density memory), and selectively coupling data lines responsive to input signals.
  • Additional Grounds: Petitioner asserted that claims 16 and 32 are obvious over Amidi. Petitioner also asserted additional obviousness challenges against claims 17, 22, 24, 26, and 33 based on the combination of Amidi and Connolly, relying on similar arguments for adding Connolly's load-isolating switches as presented in Ground 2.

4. Key Claim Construction Positions

  • "operationally coupled to": This term appears in the independent claims, describing the relationship between the PLL and other module components. Petitioner argued that since the term is not defined in the patent, its plain meaning should apply. Referencing a dictionary and the patent's figures, Petitioner proposed that the broadest reasonable interpretation is "functionally cooperating with." The petition noted that all components (PLL, register, logic element, memory devices) are on the same module and work together to perform memory operations, thus they are functionally cooperating.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 15-17, 22, 24, 26, and 31-33 of Patent 7,881,150 as unpatentable.