PTAB

IPR2015-01021

Sandisk Corp v. Netlist Inc

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1. Case Identification

2. Patent Overview

  • Title: Devices and Methods for Improving Memory Module Performance and/or Capacity
  • Brief Description: The ’536 patent describes a circuit and method for use on computer memory modules. The technology allows a module with a larger number of physical memory ranks to be used in a system that expects a smaller number of ranks by intercepting and translating control signals, thereby simulating a memory module with different characteristics (e.g., higher density) than it physically possesses.

3. Grounds for Unpatentability

Ground 1: Obviousness over Takeda, Karabatsos, and JEDEC - Claims 1, 16, 17, 24, 30, and 31 are obvious over Takeda in view of Karabatsos, and further in view of JEDEC.

  • Prior Art Relied Upon: Takeda (Japanese Application Publication No. H10-320770), Karabatsos (Patent 6,446,158), and JEDEC (JEDEC Standard 21-C).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Takeda teaches the core concept of the ’536 patent: a memory module that simulates a specific rank configuration to a computer system while physically having more ranks. Takeda’s circuit receives a smaller number of chip-select signals and generates a larger number to control its additional ranks (which Takeda calls "banks"). However, Takeda did not explicitly teach using phase-locked clock signals, selectively isolating memory loads, or storing emulated attributes. Petitioner asserted that Karabatsos, in the same field, supplied the teachings for a phase-locked loop (PLL) to provide synchronous clocking and the use of FET switches to selectively isolate the electrical load of unselected memory chips. For the dependent claims, Petitioner argued that the JEDEC standard supplied the teaching for a Serial Presence Detect (SPD) device on the module, which is configured to store attribute data (like the emulated number of ranks) for the computer system to access.
    • Motivation to Combine: A POSITA would combine Takeda's rank-emulating module with the PLL from Karabatsos to achieve better high-speed timing control, a known benefit. The POSITA would also incorporate Karabatsos's FET switches to achieve the predictable result of reduced capacitive loading and power consumption by isolating unselected memory chips. Furthermore, since Takeda itself references JEDEC standards, a POSITA would be motivated to add a JEDEC-compliant SPD to store the module's emulated attributes, ensuring the host computer's BIOS could correctly configure and interface with the simulated module.
    • Expectation of Success: Petitioner contended that combining these known elements for their established purposes was a matter of applying known techniques to a known system, which would have yielded predictable results.

Ground 2: Obviousness over Amidi and Connolly - Claims 1, 16, 17, 24, 30, and 31 are obvious over Amidi in view of Connolly.

  • Prior Art Relied Upon: Amidi (Application # 2006/0117152) and Connolly (Patent 6,070,217).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Amidi disclosed a nearly complete version of the challenged invention. Amidi described a DDR memory module that emulated a two-rank module while containing four physical ranks. Its design included a complex programmable logic device (CPLD) to manage chip-select signals, a PLL for generating phase-locked clock signals, and an SPD to store module attributes for the BIOS—disclosing the limitations of both the independent and dependent claims. Petitioner argued the only limitation not explicitly taught by Amidi was "selectively isolating a load" of the memory circuits. This missing element was supplied by Connolly, which taught using switches to decouple unselected memory chips from the data bus to reduce capacitive load.
    • Motivation to Combine: A POSITA would be motivated to integrate Connolly's well-known technique for load isolation into the memory module design of Amidi. The goal of reducing capacitive load on the memory bus was a common objective in the art, and Connolly provided a straightforward solution. Applying this to Amidi’s module would achieve the predictable benefits of reduced electrical load and lower power consumption.
    • Expectation of Success: Petitioner argued that a POSITA would have had a high expectation of success in combining Connolly's load-isolating switches with Amidi's memory module, as it represented a simple application of a known solution to a known problem.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 3) based on the combination of Takeda, JEDEC, and Connolly, which relied on similar rank-emulation and design modification theories but used JEDEC to teach a PLL and Connolly to teach load isolation.

4. Key Claim Construction Positions

  • "Rank": Petitioner argued that the term "rank" should be construed as "a block or area that is created using some or all of the memory chips on a memory module." This construction was central to the arguments, as it allowed Petitioner to equate the term "banks" as used in the Takeda reference (describing groups of memory devices on a module) with the claimed term "ranks," thereby mapping Takeda's disclosure onto the claims.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 16, 17, 24, 30, and 31 of Patent 8,081,536 as unpatentable.