PTAB

IPR2015-01233

Samsung Electronics Co., Ltd. v. Imperium (IP) Holdings

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1. Case Identification

2. Patent Overview

  • Title: Combined Single-Ended and Differential Signaling Interface
  • Brief Description: The ’290 patent relates to a data interface circuit that can be selectively configured to operate as either a single-ended interface or a differential interface. The invention purports to increase compatibility with external devices while reducing pin count and cost by combining both interfaces into a single circuit that reuses the same output pins.

3. Grounds for Unpatentability

Ground 1: Anticipation/Obviousness over Roe - Claim 1 is unpatentable under 35 U.S.C. §102 or, alternatively, obvious under 35 U.S.C. §103 over Roe.

  • Prior Art Relied Upon: Roe (Patent 5,929,655).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Roe discloses every limitation of claim 1. Roe teaches a "dual-purpose I/O circuit" that can be configured for either single-ended or differential signaling modes. Roe’s circuit explicitly includes a first single-ended interface (I/O cell 122a), a second single-ended interface (I/O cell 122b), and a differential interface (I/O cell 124), all connected to a common set of output pads (120a, 120b). The selection between single-ended and differential output is controlled by a selection signal (DIFF_EN), directly corresponding to the "selectable" limitation of claim 1.
    • Motivation to Combine (for §103 grounds): For the alternative obviousness ground, Petitioner asserted that even if Roe did not explicitly disclose an element, a person of ordinary skill in the art (POSITA) would have found it obvious to modify Roe's circuit based on its own teachings. Roe’s stated purpose was to achieve signaling compatibility for a greater variety of applications while reducing die size and I/O pin count, which aligns perfectly with the purported invention.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success as Roe’s circuit already provides the fundamental structure for selectable single-ended and differential signaling using standard, well-understood circuit components.

Ground 2: Anticipation/Obviousness over Toshiba - Claim 1 is unpatentable under §102 or, alternatively, obvious under §103 over Toshiba.

  • Prior Art Relied Upon: Toshiba (Japanese Patent Publication No. 1997-006592).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Toshiba also discloses all limitations of claim 1. Toshiba describes a semiconductor integrated circuit designed to "selectively use a differential interface and a single-ended interface without changing boards." Toshiba’s circuit uses an output buffer selecting signal (MODE_O) to select between a Gunning Transceiver Logic (GTL) single-ended output and a Low Voltage Differential Signaling (LVDS) output. Both interface types are connected to the same signal output pads (55a, 55b), thus reusing pins and fulfilling the core limitations of claim 1.
    • Motivation to Combine (for §103 grounds): The alternative obviousness argument relied on Toshiba’s explicit goal of solving the problem of limited compatibility with peripheral devices. A POSITA reading Toshiba would be motivated by its express purpose to create a selectable, versatile interface to make any minor modifications needed to arrive at the claimed invention.
    • Expectation of Success (for §103 grounds): Success would be expected, as Toshiba's design involves combining known interface standards (GTL and LVDS) in a predictable manner to achieve a known goal (interface flexibility).

Ground 3: Obviousness over Umeda in view of Roe or Toshiba - Claim 10 is obvious over Umeda in view of Roe or Toshiba.

  • Prior Art Relied Upon: Umeda (Patent 6,452,632), Roe (Patent 5,929,655), and Toshiba (Japanese Patent Publication No. 1997-006592).

  • Core Argument for this Ground:

    • Prior Art Mapping: Claim 10 recites a CMOS imaging apparatus comprising the data interface of claim 1, a CMOS image sensor, and an image processor. Petitioner argued that Umeda discloses the base system: a CMOS imaging apparatus with a CMOS image sensor (sensor 100) connected to an external image processor (video data compression circuit 400). Umeda expressly notes the need for a "high-performance, high-versatility" interface to connect its sensor to other devices. The selectable, pin-saving interface circuits of Roe or Toshiba are argued to be the missing element.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Umeda with Roe or Toshiba to satisfy Umeda's explicitly stated design goals. Umeda stresses the urgent need for a versatile, low-cost interface, and both Roe and Toshiba teach such an interface, highlighting benefits like reduced pin count and compatibility with varied standards. Umeda itself suggests using interfaces like IEEE 1394 (differential) and PC Cards (single-ended), making the combination with a circuit that supports both a logical and predictable design choice.
    • Expectation of Success (for §103 grounds): A POSITA would have a high expectation of success because combining a known type of versatile interface (from Roe or Toshiba) with a known type of imaging system (from Umeda) to achieve a known goal (versatility and cost reduction) uses standard components and design principles.

  • Additional Grounds: Petitioner asserted additional obviousness challenges against claim 10 based on Sears (Patent 6,115,482) in view of either Roe or Toshiba. These grounds relied on similar combination logic, with Sears providing a different base system (an electronic reading system with a CMOS sensor) that expressly required a cost-effective, high-throughput interface compatible with multiple standards.

4. Key Claim Construction Positions

  • "single-ended interface" / "differential interface": Petitioner adopted constructions agreed upon in related litigation: "an interface that uses a single line to transmit a signal" for single-ended, and "an interface that uses two lines to communicate a signal" for differential. This construction was argued as being consistent with the specification and sufficient for the invalidity analysis.
  • "wherein an output of the data interface circuit is selectable...": Petitioner proposed this means "wherein either the single-ended interfaces or the differential interface can be selected to output data from the data interface circuit." This construction was argued to clarify that the selection applies to the two distinct interface types taught in the patent.
  • "an image processor connected to the CMOS image sensor to receive the signals...": Petitioner proposed this term means "a processor connected to the CMOS image sensor for processing image data received from the single-ended and the differential interfaces." This construction clarifies that the "image processor" must actually process image data, a key functional aspect of the apparatus in claim 10.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1 and 10 of Patent 6,836,290 as unpatentable under §102 and/or §103.