PTAB

IPR2015-01233

Samsung Electronics Co Ltd v. Imperium IP Holdings

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Combined Single-ended and Differential Signaling Interface
  • Brief Description: The 6,836,290 patent relates to a data interface circuit that can be selectively configured to operate in either a single-ended or a differential signaling mode. The technology aims to provide compatibility with various external devices while minimizing pin count and manufacturing costs by reusing the same output pins for both signaling modes.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claim 1 - Claim 1 is anticipated under 35 U.S.C. §102 by Roe.

  • Prior Art Relied Upon: Roe (Patent 5,929,655).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Roe discloses every limitation of claim 1. Roe teaches a "dual-purpose I/O circuit" designed to support both single-ended and differential signaling modes to increase compatibility while reducing pin count. The circuit includes first and second single-ended I/O cells and a differential I/O cell, all connected to a common pair of conducting pads (output lines). A selection signal, "DIFF_EN," is used to selectively enable either the single-ended output buffers or the differential output buffer, thereby making the output selectable as required by the claim.

Ground 2: Anticipation of Claim 1 - Claim 1 is anticipated under §102 by Toshiba.

  • Prior Art Relied Upon: Toshiba (Japanese Patent Publication No. 1997-006592).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Toshiba also discloses all elements of claim 1. Toshiba describes an I/O circuit that can "selectively use a differential interface and an SE [single-ended] interface" without changing circuit boards. The circuit uses a selection signal ("MODE_O") to choose between single-ended output buffers (GTLO1, GTLO2) and a differential output buffer (LVDSO). Crucially, both interface types are connected to the same signal output pads, thus reusing pins to reduce board space and cost, directly mapping to the limitations of claim 1.

Ground 3: Obviousness of Claim 10 - Claim 10 is obvious under §103 over Umeda in view of Roe or Toshiba.

  • Prior Art Relied Upon: Umeda (Patent 6,452,632) in view of either Roe (Patent 5,929,655) or Toshiba (Japanese Patent Publication No. 1997-006592).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Umeda discloses the basic framework of claim 10: a CMOS imaging apparatus comprising a CMOS image sensor connected to an external image processor. Umeda explicitly teaches that its system requires an interface and suggests that different types, such as a single-ended "PC Card" or a differential "IEEE 1394 interface," could be used. The data interface circuit of claim 1, which claim 10 incorporates, is provided by either Roe or Toshiba.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to combine the teachings. Umeda expressly states an urgent need for a "high-performance, high-versatility" image sensor that can meet market demands while cautioning against interfaces that increase pin count and cost. Roe and Toshiba provide the exact solution: a versatile, dual-mode interface that enhances compatibility and performance while reducing pin count and cost by sharing output pins. A POSITA would have recognized the circuits of Roe or Toshiba as a known, advantageous solution to implement the flexible, cost-effective interface sought by Umeda.
    • Expectation of Success: The combination would have been a routine implementation. Both Roe and Toshiba state their versatile interface circuits can be used for "any integrated circuit" or in a "wide range of applications." Applying these known, self-contained interface solutions to Umeda’s conventional CMOS imaging system would have been a predictable integration of known components to achieve a desired, predictable result.
  • Additional Grounds: Petitioner asserted additional obviousness challenges for claim 10 based on Sears (Patent 6,115,482) in view of Roe or Toshiba. Sears discloses a CMOS sensor-based reading system that connects to a computer using various interfaces (e.g., PCMCIA or IEEE 1394), and Petitioner argued a POSITA would have been similarly motivated to incorporate the advantageous dual-mode interfaces of Roe or Toshiba to meet Sears' stated goals of high throughput, low cost, and portability.

4. Key Claim Construction Positions

  • "single-ended interface" / "differential interface": Petitioner adopted the patent owner's proposed construction for "single-ended interface" as "an interface that uses a single line to transmit a signal" and noted agreement on "differential interface" as "an interface that uses two lines to communicate a signal."
  • "wherein an output of the data interface circuit is selectable...": Petitioner proposed this term means "wherein either the single-ended interfaces or the differential interface can be selected to output data from the data interface circuit." This construction was argued to clarify that the mode of operation is selectable.
  • "an image processor connected to the CMOS image sensor...": Petitioner proposed construing "image processor" as "a processor for processing image data." This was argued to be consistent with the plain meaning and specification, clarifying the function of the processor in the context of the claimed apparatus.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1 and 10 of Patent 6,836,290 as unpatentable.