PTAB

IPR2015-01327

NVIDIA Corp v. Samsung Electronics Co Ltd

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Methods of Forming Etch Inhibiting Structures on Field Isolation Regions
  • Brief Description: The ’902 patent discloses methods for fabricating microelectronic structures to prevent damage from misaligned contact holes. The method involves forming a second, electrically isolated "dummy" patterned conductive layer with insulating sidewall spacers on a field isolation region, which acts as an etch stop to protect underlying layers during the contact hole etching process.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lee and Yasushige - Claims 1, 3-5, 7-12, 14-16, and 18 are obvious over Lee in view of Yasushige.

  • Prior Art Relied Upon: Lee (KR App. No. 1994/021255) and Yasushige (JP Pub. No. H7-86158).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Lee taught the core elements of independent claim 1, including a method to improve contact hole alignment margin by forming an etch stop layer on a field oxide region. This etch stop layer comprises insulating spacers formed on the sidewalls of a "dummy pattern" conductive layer. To the extent Lee did not explicitly state the dummy pattern was "electrically isolated," Petitioner asserted that Yasushige remedied this by teaching an explicitly "electrically isolated" dummy pattern formed on a field oxide layer to solve the identical problem of protecting the field oxide from damage during a misaligned etch.
    • Motivation to Combine: A POSITA would combine Lee and Yasushige because both references were directed to the same problem (damage to field oxide layers from misaligned contact hole etching) and proposed the same solution (using a dummy pattern as an etch stop). Yasushige’s explicit disclosure of an electrically isolated dummy pattern would have been seen as a natural and advantageous feature to incorporate into Lee’s method, as a non-functional mechanical structure should not have unnecessary electrical connections.
    • Expectation of Success: The combination involved applying known semiconductor fabrication techniques to address a well-understood problem, which would have provided a POSITA with a high expectation of success.

Ground 2: Obviousness over Lee, Yasushige, and Nowak - Claims 2 and 17 are obvious over Lee in view of Yasushige and Nowak.

  • Prior Art Relied Upon: Lee (KR App. No. 1994/021255), Yasushige (JP Pub. No. H7-86158), and Nowak (Patent 4,916,514).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address dependent claims 2 and 17, which further required the "insulating layer" (into which the contact hole is etched) to comprise nitride. Petitioner argued that while Lee and Yasushige taught forming such an insulating layer, Nowak explicitly disclosed the well-known practice of using silicon nitride (Si3N4) or oxynitride as the material for a conformal insulating layer covering dummy conductors.
    • Motivation to Combine: A POSITA implementing the method of Lee and Yasushige would have to select a material for the insulating layer. Using nitride was an obvious design choice, as it was one of a limited number of well-known insulating materials used in semiconductor fabrication. Nowak confirmed it was known to use nitride for this purpose, particularly where high etch selectivity against oxide-based spacers (as taught in Lee) was desired.
    • Expectation of Success: The use of silicon nitride as an insulating layer was a standard, predictable, and routine practice in the art.

Ground 3: Obviousness over Lee, Yasushige, and the ’524 Patent - Claims 6 and 13 are obvious over Lee in view of Yasushige and the ’524 patent.

  • Prior Art Relied Upon: Lee (KR App. No. 1994/021255), Yasushige (JP Pub. No. H7-86158), and the ’524 patent (Patent 4,952,524).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground also built upon Ground 1 to address dependent claims 6 and 13, which added the limitation of "forming a trench in said substrate" where the "field isolation layer fills said trench." Petitioner contended that while Lee disclosed a field oxide layer for isolation, the ’524 patent taught forming such isolation layers using trench isolation techniques, a well-known alternative to traditional LOCOS methods.
    • Motivation to Combine: A POSITA would combine these teachings because trench isolation, as taught by the ’524 patent, was known to consume less space and avoid the "bird's beak" encroachment common with LOCOS methods. This advantage directly furthered the central goal of Lee's invention—improving alignment margins in increasingly smaller integrated circuits. Using a space-saving isolation technique was a logical and obvious improvement to Lee's process.
    • Expectation of Success: Trench isolation was a conventional and well-understood technique for device isolation, making its integration into the process of Lee and Yasushige entirely predictable.

4. Key Claim Construction Positions

  • "insulating spacer along a sidewall of the [second] patterned conductive layer": Petitioner argued this term should be construed to include the functional limitation "that prevents etch damage to the field isolation layer if the contact hole is misaligned." This construction was asserted to be required by the patent’s specification and prosecution history, which consistently characterized the invention's purpose as solving the contact misalignment problem.
  • "an insulating layer" and "forming a trench...": Petitioner contended these terms had a plain and ordinary meaning. However, Petitioner also noted that the cited prior art would anticipate the claims even under the constructions for these terms proposed by the Patent Owner in a related district court litigation.

5. Relief Requested

  • Petitioner requested institution of an inter partes review for claims 1-18 of the ’902 patent and cancellation of those claims as unpatentable.