PTAB

IPR2015-01524

Samsung Electronics Co., Ltd. v. Elbrus International Limited

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1. Case Identification

2. Patent Overview

  • Title: Data Transfer Arrangement
  • Brief Description: The ’130 patent is directed to a data transfer scheme for electronic circuits. The scheme includes two bus drivers, a voltage precharge source, complementary bus lines, and a two-stage latching sense amplifier intended to improve the speed and reliability of data transmission.

3. Grounds for Unpatentability

Ground 1: Claims 1-2, 5-6, and 9 are obvious over Sukegawa in view of Lu.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241) and Lu (an August 1984 IEEE Journal article).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sukegawa discloses a complete data transfer arrangement with nearly all features of independent claim 1, including two bus drivers, a differential bus, and a latching sense amplifier with a first stage and an output stage. However, while Sukegawa teaches precharging its main differential bus to an intermediate voltage (Vdd/2), it discloses precharging the subsequent differential data bus (within the sense amplifier) to a full supply voltage (Vdd).
    • Motivation to Combine: Lu was cited for its explicit teaching on the benefits of precharging bitlines to an intermediate "half-VDD" voltage, which achieves faster sensing by reducing the required voltage swing. Petitioner asserted a person of ordinary skill in the art (POSITA) would apply Lu's well-understood technique to the differential data bus of Sukegawa's circuit to achieve the same predictable benefit of increased operational speed.
    • Expectation of Success: The combination involved applying a known technique (Lu's half-Vdd precharge) to a known circuit type (Sukegawa's) to obtain the predictable result of faster performance.
    • Key Aspects: Petitioner contended that Sukegawa also inherently teaches the limitations of dependent claims 2 (active pull-up/pull-down drivers), 5 (precharging to an intermediate voltage), 6 (a precharge circuit), and 9 (cross-coupled feedback in the output stage).

Ground 2: Claim 3 is obvious over Sukegawa, Lu, and Watanabe.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241), Lu (an August 1984 IEEE Journal article), and Watanabe (Patent 6,108,254).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon the combination of Sukegawa and Lu. Claim 3 adds specific structural limitations to the "first stage" of the latching sense amplifier, requiring a plurality of input pass transistors and a specific arrangement of cross-coupled NMOS and PMOS transistors coupled to clock signals and inputs. Petitioner asserted that Watanabe discloses a data latch circuit with a "first stage" that contains these exact structural features.
    • Motivation to Combine: A POSITA would be motivated to substitute the first stage of the Sukegawa/Lu combination with the more efficient first stage from Watanabe. The petition argued Watanabe’s design was superior because it used fewer transistors and control signals, resulting in a faster, smaller circuit layout, which were well-known and highly desirable design goals in the field of integrated circuits.
    • Expectation of Success: This modification was presented as a simple substitution of one known, improved circuit block (Watanabe's first stage) for another (Sukegawa's) to gain a predictable improvement in speed and circuit density.

Ground 3: Claim 7 is obvious over Sukegawa, Lu, and Hardee.

  • Prior Art Relied Upon: Sukegawa (Patent 5,828,241), Lu (an August 1984 IEEE Journal article), and Hardee (Patent 6,249,469).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground also builds on the base combination of Sukegawa and Lu. Claim 7, which depends from claim 2, requires that the active pull-up and active pull-down bus drivers both be NMOS transistors. Sukegawa’s bus drivers are CMOS, using PMOS transistors for pull-up and NMOS transistors for pull-down. Hardee was cited for explicitly teaching the use of all-NMOS transistors for both pull-up and pull-down driver functions in a similar memory circuit.
    • Motivation to Combine: A POSITA would modify the CMOS drivers in the Sukegawa/Lu combination to use the all-NMOS driver design taught by Hardee. The stated motivations were to reduce circuit layout area (by eliminating the need for PMOS n-wells) and to improve immunity to latch-up, both of which were known advantages of all-NMOS designs over CMOS in certain applications.
    • Expectation of Success: Petitioner argued this was a simple, well-understood design choice, substituting one known driver type for another to achieve predictable and desirable benefits.

4. Key Claim Construction Positions

  • latching sense amplifier: Petitioner proposed this term be construed as "a circuit, including a latch, that detects and amplifies signals." This broad construction was argued to be critical for establishing that prior art circuits like Sukegawa's, which perform these functions, fall within the scope of the claim, even if not explicitly named as such.
  • stage: Petitioner proposed this term be construed as "portion of a circuit." This construction was central to its argument that it could identify distinct "first stage" and "output stage" portions within the single, integrated receiver circuit of the prior art, thereby satisfying the two-stage structure required by claim 1.

5. Arguments Regarding Discretionary Denial

  • Petitioner disclosed it was concurrently filing a second IPR petition against the same patent. It argued against discretionary denial by asserting that the two petitions present "independent, distinctive, and non-redundant grounds." This petition focused on obviousness combinations under 35 U.S.C. §103, while the other presented an anticipation ground based on a different primary reference, which Petitioner claimed would require different arguments and evidence from the Patent Owner to rebut.

6. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-7, and 9 of the ’130 patent as unpatentable.