PTAB

IPR2015-01620

LG Electronics Inc v. ATI Technologies ULC

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1. Case Identification

2. Patent Overview

  • Title: Efficient Time Shifting of a Multiplexed Packetized Data Stream
  • Brief Description: The ’945 patent discloses a method and system for efficiently time-shifting digital video data. The invention relates to receiving a multiplexed packetized data stream, such as an MPEG transport stream, and enabling functions like pausing and replaying live programs by storing and retrieving the stream data.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hatanaka and Hoogenboom - Claim 21 is obvious over Hatanaka in view of Hoogenboom.

  • Prior Art Relied Upon: Hatanaka (Patent 6,397,000) and Hoogenboom (Patent 5,517,250).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hatanaka discloses a base system for digital video recording and playback that meets most limitations of claim 21. Hatanaka teaches a device with a demultiplexer to select data packets, a storage device to record them, a clock recovery module to regenerate a clock from the incoming stream, and a decoder to process the data for playback. However, Petitioner contended that Hatanaka’s clock recovery method could be improved. Hoogenboom was asserted to supply the missing element: generating a clock based on timing information before the selected packets are stored. Hoogenboom teaches a more efficient scheme where timing information, like a Decode Time Stamp (DTS), is extracted from a packetized elementary stream (PES) header and appended to the picture information for storage. This allows the data to be decoded later without reaccessing the original PES header.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Hatanaka and Hoogenboom because both references address the same problem of improving the efficiency of decoding stored digital video signals. Hoogenboom’s solution of extracting and appending timing information prior to storage was presented as a known method for achieving a simpler, more robust, and faster system. A POSITA would have recognized this benefit and modified Hatanaka's system with Hoogenboom’s teachings to improve its performance.
    • Expectation of Success: Petitioner asserted that a POSITA would have a reasonable expectation of success because both Hatanaka and Hoogenboom operate in the same technical field (MPEG-2 video streaming) and use compatible components and data structures, such as transport streams, Program Clock References (PCRs), and time stamps. The integration was described as a straightforward application of a known technique to an existing system.

Ground 2: Obviousness over Hatanaka and Anderson - Claim 21 is obvious over Hatanaka in view of Anderson.

  • Prior Art Relied Upon: Hatanaka (Patent 6,397,000) and Anderson (Patent 6,275,507).
  • Core Argument for this Ground:
    • Prior Art Mapping: As in Ground 1, Hatanaka was asserted to provide the foundational digital recording and playback system. Petitioner introduced Anderson to supply the teaching of performing clock recovery before data is stored in memory, but for a different reason than Hoogenboom. Anderson explicitly discloses a transport demultiplexer with "front end" logic that includes a clock recovery unit and a "back end" logic that includes a packet buffer (memory). Anderson teaches that performing functions like clock recovery on the front end, before storage, serves to "reduce the load on the application processor" and minimize memory requirements. Petitioner argued it would be obvious to apply Anderson's front-end clock recovery architecture to Hatanaka's system.
    • Motivation to Combine: Petitioner contended that a POSITA would combine Hatanaka and Anderson to improve system performance. Anderson expressly identifies a "clear need" for transport demultiplexers to perform front-end processing, including clock recovery, to minimize the host processor's load. A POSITA seeking to optimize the Hatanaka system would be motivated by Anderson's teachings to move the clock recovery function before the storage step to gain the known benefits of reduced processing overhead and more efficient memory use.
    • Expectation of Success: A POSITA would expect the combination to succeed as both references describe systems for processing compressed MPEG-2 streams and use similar timing information like PCRs extracted from packet headers for clock recovery. The combination represented the application of a known design choice (front-end processing) to improve a similar system.

4. Relief Requested

  • Petitioner requested the institution of an inter partes review and cancellation of claim 21 of the ’945 patent as unpatentable.