PTAB

IPR2015-01811

Intel Corp v. Memory Integrity LLC

Key Events

Petition

petition

Title: Techniques for Processing Memory Transactions
Brief Description: The ’254 patent describes techniques for addressing a "bottleneck" in processing memory transactions in computer systems containing multiple clusters of processors. The invention purports to solve this by dividing the processing workload among multiple "protocol engines" based on whether a memory transaction targets local or remote memory.

Prior Art Relied Upon: Pragaspathy ("Address Partitioning in DSM Clusters with Parallel Coherence Controllers," IEEE, Oct. 2000).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Pragaspathy, published more than two years before the ’254 patent’s priority date, discloses every limitation of claims 1 and 8. Pragaspathy identifies the same "communication bottleneck" caused by a single protocol engine and proposes the same solution: partitioning the workload between multiple protocol engines (which it calls finite state machines or "FSMs") based on the memory transaction's target address. Specifically, Pragaspathy teaches using one set of FSMs for local ("home") memory events and a separate, distinct set for remote memory events. It further discloses selection circuitry (an "address demultiplexer") that uses address bits to route transactions to the appropriate FSM, thereby satisfying the limitations of independent claim 1. For claim 8, Petitioner asserted that Pragaspathy's distinct sets of protocol engines for local and remote memory are inherently mutually exclusive.
- Key Aspects: The core of this ground is that Pragaspathy, which was not considered during prosecution, allegedly describes the exact architecture claimed in the ’254 patent to solve the exact same problem.

Prior Art Relied Upon: Pragaspathy and Culler ("Parallel Computer Architecture," a 1999 textbook).
Core Argument for this Ground:
- Prior Art Mapping: This ground addresses dependent claims 2-5, which add limitations regarding specific interconnect architectures (point-to-point, ring, mesh) and the use of packets for memory transactions. Petitioner contended that while Pragaspathy discloses a bus-based system, Culler is a textbook that extensively details various multiprocessor architectures. Culler explicitly teaches that bus-based systems have scalability limitations and describes point-to-point networks (including ring and mesh topologies) as well-known, scalable alternatives. Culler also teaches that memory requests are typically transmitted in packets.
- Motivation to Combine: A POSITA would combine Culler's teachings with Pragaspathy's system to improve performance and scalability. Replacing Pragaspathy's bus with a scalable point-to-point interconnect from Culler was argued to be a predictable design choice to overcome the known scaling limits of bus architectures.
- Expectation of Success: A POSITA would have a high expectation of success, as implementing a point-to-point interconnect was a well-understood technique for which Culler provided detailed implementation guidance.

Prior Art Relied Upon: Pragaspathy, Culler, and Bauman (Patent 6,415,364).
Core Argument for this Ground:
- Prior Art Mapping: This ground targets dependent claim 6, which requires the selection circuitry to be located within at least one of the processing nodes. In Pragaspathy, the selection circuitry is part of a central interconnection controller. Bauman, however, discloses a multiprocessor system where each processing node contains its own switching circuitry (a crossbar module) that routes memory requests based on address information.
- Motivation to Combine: Petitioner argued that the location of selection circuitry is a simple design choice with a finite number of predictable options (e.g., centralized or distributed). A POSITA, seeking to implement the Pragaspathy/Culler system, would look to known configurations like that in Bauman and would be motivated to place the selection circuitry within the processing nodes for design-specific reasons.
- Expectation of Success: A POSITA would expect success in relocating the circuitry, as it represented the application of a known design principle to a known system component.
Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 7 based on the combination of Pragaspathy, Culler, and Piranha (a 2000 ACM article), which taught a dedicated protocol engine for processing interrupts.

Petitioner argued for a specific construction of the claim phrase "a...protocol engine...corresponding to one of local and remote memory."
- Proposed Construction: "a...protocol engine configured to be assigned addresses for one of either local or remote memory in a global memory space."
- Rationale: Petitioner asserted this construction is required by the plain language ("one of" means one, not both), the specification's consistent description of separate "local" and "remote" engines, and the prosecution history. During prosecution, the patent owner allegedly distinguished the invention from prior art by emphasizing the "unique nature" of assigning protocol engines to either local or remote memory subsets, thereby surrendering a broader interpretation. This construction is critical to the anticipation argument against Pragaspathy, which explicitly teaches such a division.

Petitioner requests institution of an inter partes review and cancellation of claims 1-8 of the ’254 patent as unpatentable under 35 U.S.C. §§ 102 and/or 103.