Apple Inc v. Longitude Flash Memory Systems SARL

1. Case Identification

• Case #: IPR2015-01908
• Patent #: 8,050,095
• Filed: September 14, 2015
• Petitioner(s): Apple Inc.
• Patent Owner(s): Longitude Flash Memory Systems S.A.R.L.
• Challenged Claims: 1-9, 11-14

2. Patent Overview

• Title: Flash Memory Data Correction and Scrub Techniques
• Brief Description: The ’095 patent discloses methods for operating non-volatile flash memory systems by performing background "housekeeping operations," such as data scrubbing and wear leveling. The patented technology centers on monitoring patterns of host activity to enable or defer these non-essential background operations, aiming to execute them during periods of low host activity to improve overall system performance.

3. Grounds for Unpatentability

Ground 1: Anticipation by Wells - Claims 1-9 and 11-14 are anticipated by Wells.

• Prior Art Relied Upon: Wells (Patent 5,341,339).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Wells discloses every limitation of the challenged claims. Wells teaches a flash memory system that performs a background "cleanup operation" to manage memory blocks, which Petitioner contended is a type of "housekeeping operation" as claimed (specifically, a wear-leveling operation). Wells's system monitors the state of the memory, which is a direct result of host write activity. It identifies a first pattern of host activity—when the ratio of "dirty" to total memory space exceeds a predefined threshold (e.g., 80%)—and in response, enables the cleanup operation. When this threshold is not met (a second pattern), the cleanup operation is not enabled. For claims centered on host interrupts (e.g., claim 5), Petitioner argued that Wells teaches that its cleanup process is interruptible by the host. A host interrupt request (a parameter of host activity) is a predefined condition that causes the cleanup operation to be halted (not enabled) to service the host's request. In the absence of an interrupt, the cleanup operation is enabled to proceed.
  • Key Aspects: The core of the argument rested on equating Wells's background, interruptible "cleanup operation," which is triggered by memory state, with the ’095 patent's claimed "housekeeping operation" that is enabled based on "patterns of host activity."

Ground 2: Anticipation by Swaminathan - Claims 1-3 and 5-9 are anticipated by Swaminathan.

• Prior Art Relied Upon: Swaminathan (Application # 2003/0046487).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Swaminathan teaches a method of refreshing (or scrubbing) data in a flash memory system that anticipates the claims. Swaminathan's system monitors host activity by using counters to track the number of programming or erase operations on memory sectors. This tracking constitutes "monitoring patterns of activity of the host." When a counter reaches a predetermined threshold (a "first pattern of host activity"), a data refresh operation is enabled. If the counter is below the threshold (a "second pattern"), the refresh is not enabled. Critically, Swaminathan explicitly addresses avoiding memory unavailability during refresh by allowing the host processor to continue accessing memory between refresh operations. Petitioner mapped this to claim 5 by arguing that Swaminathan determines a parameter of host activity (whether the host processor is performing an operation). If the host is active (the predefined condition is met), the housekeeping operation is not enabled (i.e., it is paused or interleaved). If the host is inactive, the housekeeping operation is enabled for execution.

Ground 3: Obviousness over Wells/Swaminathan and Series 2 - Claims 4 and 11-14 are obvious over Wells or Swaminathan in view of Series 2.

• Prior Art Relied Upon: Wells (Patent 5,341,339), Swaminathan (Application # 2003/0046487), and Series 2 (Intel Series 2 Flash Memory Cards Data Sheet).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground served as an alternative to the anticipation arguments, addressing specific limitations in system claims 11-14 and method claim 4. Petitioner argued that to the extent the preamble of claim 11 ("removably connected with a host system") was found limiting, it would have been obvious to apply the memory management teachings of Wells or Swaminathan to a removable flash memory card. Likewise, for claim 4's requirement of using logical addresses, Petitioner contended this was an obvious implementation detail.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings of Wells or Swaminathan with the well-known form factor of a removable memory card, as disclosed in the Series 2 data sheet, to create a practical and commercially relevant product. Series 2 also expressly teaches using a flash translation layer to allow a host to interact with the memory using logical addresses, providing a clear motivation to implement this standard feature in the systems of Wells or Swaminathan to ensure compatibility with conventional host systems.
  • Expectation of Success: A POSITA would have had a high expectation of success, as combining known software-based memory management techniques with standard hardware interfaces and form factors was a routine and predictable design choice in the field.

4. Key Claim Construction Positions

• "housekeeping operation": Petitioner argued this term is not one of art and, based on the claim language (e.g., claim 7 mentioning "wear leveling or scrub"), should be construed to mean an operation implemented by the memory system, such as wear leveling or data scrubbing, that is not performed in direct response to a command received from the host. This construction was critical for mapping the background maintenance tasks in the prior art to the claims.
• "host": Based on the specification's definition, Petitioner proposed construing "host" as "a system that connects to, or has embedded within it, the memory system." This broad construction was important for arguing that the controllers and processors described in the prior art systems met the "host" limitation.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-9 and 11-14 of Patent 8,050,095 as unpatentable.