Apple Inc v. Longitude Flash Memory System SARL

1. Case Identification

• Case #: IPR2015-01909
• Patent #: 7,120,729
• Filed: September 14, 2015
• Petitioner(s): Apple Inc.
• Patent Owner(s): Longitude Flash Memory Systems S.A.R.L.
• Challenged Claims: 15-17

2. Patent Overview

• Title: Automated Wear Leveling in Non-Volatile Storage Systems
• Brief Description: The ’729 patent discloses methods and systems for performing automated wear leveling in non-volatile storage systems, such as flash memory. The core technique involves maintaining a collection of temporarily unused, erased blocks, described as an "erased block pool," to facilitate the exchange of data from high-wear blocks to low-wear blocks to evenly distribute program/erase cycles.

3. Grounds for Unpatentability

Ground 1: Anticipation over Wells - Claims 15-17 are anticipated by Wells under 35 U.S.C. §102.

• Prior Art Relied Upon: Wells (5,341,339).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Wells, which issued over nine years before the ’729 patent was filed, describes a wear-leveling technique that is substantially identical to the method claimed. Wells taught maintaining a reserve of erased blocks for cleanup operations, which corresponds to the claimed "erased block pool." For wear leveling, Wells disclosed identifying the "best block to clean up" by evaluating factors including the number of erase cycles, which meets the limitation of identifying a block for exchange. The process involved copying valid data from the identified block to free space in the reserved erased blocks, updating mapping tables, erasing the now-empty original block, and returning it to the pool of available clean blocks for future use. This process, Petitioner asserted, disclosed every limitation of independent claim 15 and dependent claims 16-17.

Ground 2: Obviousness over Linux Publication and POSITA Knowledge - Claims 15-17 are obvious over the Linux publication in view of the PC Card Standard under 35 U.S.C. §103.

• Prior Art Relied Upon: The Linux publication (pcmcia-cs package version 3.1.21 by David Hinds) and the PC Card Standard (Media Storage Formats Specification, Volume 7, 1999).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that the Linux publication, a driver package for PCMCIA-compliant hardware, disclosed a wear-leveling algorithm within its Flash Translation Layer (FTL) implementation that rendered the claims obvious. The publication's reclaim_block() function described a wear-level exchange using two types of blocks: "data units" (storing user data) and "transfer units" (forming an erased block pool). The algorithm identified a "data unit" for exchange by cycling through all available data units in a for loop to find the one with the lowest erase count ("oldest data unit"). This identified data unit was then exchanged with a "transfer unit" from the pool by copying its contents via the copy_erase_unit() function. This function also updated the logical-to-physical mapping by swapping block pointers ("Offset" parameters). Finally, the original data unit was erased and returned to the pool of "transfer units."
  • Motivation to Combine: A POSITA would combine the Linux publication with the general knowledge evidenced by the PC Card Standard because the publication was designed to implement that standard. The well-known issue of long erase times in flash memory, a key consideration in the PC Card Standard, would motivate a POSITA to implement a pool of pre-erased blocks ("transfer units") to avoid performance bottlenecks. The Linux publication’s explicit algorithm for selecting the "best" data unit from a plurality of units would further motivate a POSITA to configure the system with such a plurality to realize the benefits of the wear-leveling selection logic.
  • Expectation of Success: A POSITA would have had a high expectation of success, as combining a driver’s FTL wear-leveling logic with the standards it was designed to support represented a straightforward application of known principles to solve a known problem (performance degradation from erase latency) in flash memory management.

4. Key Claim Construction Positions

• "the plurality of blocks maintained as an erased block pool" (claim 15): Petitioner proposed construing this term as "a plurality of blocks kept in existence continually as a collection of temporarily unused but physically erased blocks." This construction was argued to be consistent with the specification and the common understanding in the art, clarifying that the pool is a persistent feature of the system used for wear-leveling exchanges.
• "identifying at least one of the plurality of physical blocks at a time" (claim 15): Petitioner proposed this means "identifying, one at a time, at least one of a plurality of physical blocks." This construction emphasized that the evaluation and selection process for a wear-level exchange is performed on an individual, block-by-block basis, which Petitioner contended was explicitly taught by the prior art’s use of iterative loops to find the best candidate block.

5. Relief Requested

• Petitioner requested the Board institute an inter partes review of claims 15-17 of the ’729 patent and cancel those claims as unpatentable.