PTAB

IPR2015-01911

Apple Inc v. Longitude Flash Memory Systems SARL

Key Events

Petition

petition Intelligence

Title: Power Management Block for Use In A Non-Volatile Memory System
Brief Description: The ’611 patent describes a method and system for managing the power-up sequence of a non-volatile memory system. The system determines if a previous power-down was normal or abnormal by checking for one or two "signatures" in a reserved memory area and, based on the result, either enables the memory for use or initiates a recovery or initialization process.

Prior Art Relied Upon: Culbert (Patent 5,557,777).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Culbert discloses every limitation of the challenged claims. Culbert describes a system for recovery from power loss in devices with non-volatile memory. Upon power-up, Culbert checks a "protection register" to determine if the prior shutdown was "orderly" (value=0) or "non-orderly" (value≠0). This register, stored in non-volatile memory, directly corresponds to the ’611 patent’s claimed "reserved memory area" and "first signature" indicating a normal power-down. If the shutdown was orderly, Culbert enables the memory for use. If not, it performs a recovery process, such as resetting the CPU and initializing memory tables, which corresponds to the ’611 patent’s "first process" performed after an abnormal shutdown. Dependent claims requiring a second signature (indicating prior initialization) were allegedly met by Culbert’s "successful store register," which indicates data was successfully written to non-volatile memory.

Prior Art Relied Upon: Culbert (Patent 5,557,777) and the general knowledge of a Person of Ordinary Skill in the Art (POSA).
Core Argument for this Ground:
- Prior Art Mapping: This ground incorporated the anticipation arguments from Ground 1 and further addressed claims 10 and 25, which require the non-volatile memory to be NAND flash memory. Petitioner contended that Culbert’s teachings are not specific to any particular type of non-volatile memory.
- Motivation to Combine: A POSA at the time of the invention would have recognized that NAND flash memory was a common, commercially available, and reliable type of non-volatile memory. Therefore, a POSA would combine Culbert’s power-down recovery system with NAND flash memory as a simple substitution of one known element for another to yield predictable results.
- Expectation of Success: The substitution would have been straightforward, with a high expectation of success, as using NAND flash memory was a well-established practice for non-volatile storage.

Prior Art Relied Upon: Lasser (Patent 6,510,488).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Lasser discloses a system for a "fast wake-up" of flash memory that anticipates the challenged claims. Lasser’s system determines if a device underwent an "orderly shut down" or a "non-orderly exit." This determination is made by checking a "validity flag" stored in the flash memory. If the flag indicates a valid state (orderly shutdown), Lasser uses existing memory translation tables for a fast start-up. This corresponds to the ’611 patent’s method of checking a signature and enabling the memory for use. If the flag is invalid (non-orderly shutdown), Lasser initiates a "regular wake-up procedure" to ensure data integrity, which maps to the ’611 patent’s "first process" of recovery or initialization. Lasser’s teaching of setting the flag to an invalid state upon wake-up to protect against subsequent unexpected shutdowns was argued to function as the second signature required by dependent claims.
Additional Grounds: Petitioner asserted additional obviousness challenges (Ground 4) against claims 10 and 25 over Lasser in view of general POSA knowledge. This argument relied on the same design modification theory as Ground 2: that a POSA would have been motivated to implement Lasser’s generic flash memory system using the well-known and reliable NAND flash technology.

"Substantially Normal Power Down Process": Petitioner argued that because the ’611 patent does not define this term, it should be interpreted for the purpose of the IPR as a "normal power down process."
"Initialization Process": Petitioner noted that the patent’s definition of this term is open-ended ("may include, but is not limited to..."). For its analysis, Petitioner mapped this claim limitation to the prior art’s disclosure of creating or building memory address translation tables, a process a POSA would understand as a form of memory initialization.
"Code Devices": Petitioner contended that a POSA would interpret this term under 35 U.S.C. §112(6) as a means-plus-function limitation. Accordingly, Petitioner analyzed the prior art by interpreting "code devices" as software code executed by a hardware controller.

Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 3, 4, 10, 17, 19, 20, 23, 24, and 25 of the ’611 patent as unpatentable.