PTAB

IPR2015-01994

Linear Technology Corp v. In Depth Test LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Methods and Apparatus for Semiconductor Testing
  • Brief Description: The ’373 patent discloses systems and methods for testing semiconductors by analyzing test data to identify "outliers." The technology uses a tester connected to a computer to find test results that are within specification limits but deviate from a desired range, and then generates an output report including the identified outliers.

3. Grounds for Unpatentability

Ground 1: Anticipation by Sun - Claims 1, 2, 4, 5, 7-9, 11, 12, and 14 are anticipated by Sun.

  • Prior Art Relied Upon: Sun (Patent 6,240,329).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sun discloses every element of the challenged claims. Sun teaches a complete test system comprising a wafer tester connected to a computer that receives and analyzes test data. Critically, Petitioner asserted that Sun’s "out of control" test result—defined as a result that is within upper and lower specification limits but outside of preferred control limits—is the same as the ’373 patent’s claimed "outlier." Sun’s system generates and stores summary tables that identify these "out of control" results using a specific symbol, which Petitioner argued constitutes the claimed "output report including the identified outlier." For dependent claims, Petitioner contended that Sun’s use of lot-level summary tables and rule files to store control limits constitutes a "recipe file" (claims 2, 9), its adjustment of target values based on wafer-specific measurements is "automatic calibration" (claims 4, 11), its "expert system" for comparing different test results to find a defect’s cause is a "data correlation element" (claims 5, 12), and its averaging of multiple data points is a "data smoothing element" (claims 7, 14).

Ground 2: Anticipation by Madge - Claims 1-5, 7-12, and 14 are anticipated by Madge.

  • Prior Art Relied Upon: Madge (Patent 6,598,194).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Madge discloses a system for testing ICs on a wafer that meets all limitations of the challenged claims. Madge describes a tester connected to a computer that receives test data and identifies ICs that stray significantly from a norm. Petitioner specifically pointed to Madge’s teaching of assigning a lower "grade of passing code" to "ICs with relatively larger offsets, but not so large as to be classified as an outlier [i.e., a failed device]." Petitioner argued this concept is a direct disclosure of the ’373 patent’s "outlier." Madge then generates a wafer map showing these grades, which serves as the claimed "output report." For dependent claims, Petitioner asserted that Madge’s use of parameter files meets the "recipe file" limitation (claims 2, 9), its analysis based on regional groupings of ICs (e.g., concentric rings) meets the "section group" limitation (claims 3, 10), and its use of a reference value derived from a subset of ICs to set pass/fail criteria for other ICs in the same region constitutes "automatic calibration" (claims 4, 11).

Ground 3: Obviousness over Sun and O'Donoghue - Claims 6, 13, 15, 16, and 18-20 are obvious over Sun in view of O'Donoghue.

  • Prior Art Relied Upon: Sun (Patent 6,240,329) and O'Donoghue (Patent 5,497,381).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Sun teaches all limitations of these claims except for performing the outlier identification "at run time." The combination with O'Donoghue was asserted to render this limitation obvious. O'Donoghue was cited for its explicit teaching of analyzing IC defect data in "real time" to provide immediate feedback for correcting systematic manufacturing process defects. Petitioner equated O'Donoghue's "real time" analysis with the ’373 patent’s "at run time" limitation.
    • Motivation to Combine: A POSITA would combine Sun's automated testing system with O'Donoghue's real-time analysis to improve manufacturing efficiency and yield. Petitioner argued that outlier analysis is a necessary "blocking" step in production, as it is used to bin (sort) wafers. Delaying this step creates a production bottleneck, lowering productivity. O'Donoghue taught that real-time analysis solves this exact problem by allowing for rapid process corrections, providing a clear motivation to apply its teachings to a system like Sun's.
    • Expectation of Success: The combination was argued to be predictable. O'Donoghue stated that sufficient computing power for real-time analysis was available well before the ’373 patent’s priority date, meaning a POSITA would have faced no technical hurdles in implementing Sun’s analysis "at run time" and would have expected the benefit of increased efficiency.

  • Additional Grounds: Petitioner asserted that claims 3 and 10 are obvious over Sun in view of Friedman (Patent 5,240,866) to teach analyzing data by wafer section group. Petitioner also asserted that claims 6, 13, and 15-20 are obvious over Madge in view of O'Donoghue, using a similar "at run time" rationale as in Ground 3.

4. Key Claim Construction Positions

  • "outlier": Petitioner argued for the construction "a test result that strays from a target value, but does not exceed specification limits or otherwise fail to be detected." This construction was asserted to be broader than a potential Patent Owner position requiring parameters to be statistically derived from the devices currently under test. Petitioner contended the ’373 patent specification allows for outliers to be identified by comparison to user-defined or pre-set thresholds stored in a recipe file. Petitioner also noted that the Board, in a related IPR, had construed the term as "a test result that is within the upper and lower limits of the product's specifications... but nevertheless strays from values which are statistically similar."

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of Patent 6,792,373 as unpatentable.