Micron Technology Inc v. Limestone Memory Systems LLC

1. Case Identification

• Case #: IPR2016-00093
• Patent #: 5,805,504
• Filed: October 26, 2015
• Petitioner(s): Micron Technology, Inc.
• Patent Owner(s): Limestone Memory Systems LLC
• Challenged Claims: 1-2

2. Patent Overview

• Title: Synchronous Semiconductor Memory Having A Burst Transfer Mode With A Plurality Of Subarrays Accessible In Parallel Via An Input Buffer
• Brief Description: The ’504 patent relates to a synchronous semiconductor memory designed to improve the speed of burst write operations. The disclosed invention addresses inefficiencies in prior art systems by using an input buffer with cascade-connected shift registers that convert serial input data to parallel data using only a clock signal, without first needing a column address. The column address is only used later to steer the stored parallel data from the registers to a plurality of internal data buses.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 are obvious over Watanabe in view of Iwama.

• Prior Art Relied Upon: Watanabe (Patent 5,581,746) and Iwama (Japanese Patent Application H4-326138).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Watanabe disclosed nearly all elements of the claimed synchronous memory, including a burst write function, parallel memory sub-arrays, internal data buses, and an input buffer that converts serial data to parallel data for distribution. The primary distinction was that Watanabe used a series of write register gates, not cascade-connected registers, for the serial-to-parallel conversion. Petitioner asserted that Iwama, which addresses the same technical problem, explicitly taught the missing element: an input buffer comprising a plurality of cascade-connected shift registers for converting serial data to parallel data in response to a clock signal. By substituting Iwama’s conventional shift register into Watanabe's otherwise complete architecture, all limitations of independent claim 1 were met. For dependent claim 2, Petitioner mapped the "buffer output control means" limitation to Watanabe's write enable circuitry (controlled by signal XW), which transfers data from the registers to the internal even and odd data buses in synchronism with the system clock.
  • Motivation to Combine: A POSITA would combine Watanabe and Iwama because both references were directed to solving the identical technical problem of increasing memory access speeds to match faster CPUs. Iwama's cascade-connected shift register was presented as a well-known, conventional component that performed the exact function required in Watanabe's system. Therefore, substituting Iwama's established circuit into Watanabe's architecture represented a simple substitution of one known element for another to achieve the predictable and desired result of efficient serial-to-parallel data conversion. This was characterized as a simple design choice, not an inventive step.
  • Expectation of Success: Because the combination involved replacing a functional block in Watanabe (write register gates) with a well-known, functionally equivalent block from Iwama (cascade shift registers), a POSITA would have had a high expectation of success in creating a functional and improved memory device.

4. Key Claim Construction Positions

Petitioner argued that two key terms in the challenged claims should be construed as means-plus-function limitations under 35 U.S.C. §112 ¶ 6, as the term "means" is a nonce word lacking sufficient structural definition.

• "register output selecting means ... for distributing said received parallel data signals..." (claims 1-2): Petitioner contended this term was drafted in traditional means-plus-function format. It proposed that the corresponding structure disclosed in the ’504 patent for performing the stated function is a plurality of transfer gate transistors that are responsive to the column address to selectively distribute data in parallel to either the even or odd internal buses.
• "buffer output control means for transferring said outputs..." (claim 2): Petitioner similarly argued this term is a means-plus-function limitation. It identified the corresponding structure in the ’504 patent as a plurality of transfer gate transistors responsive to a buffer output control signal (e.g., IOW) for transferring data from the output selector to the internal data buses.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1 and 2 of Patent 5,805,504 as unpatentable.