PTAB

IPR2016-00095

Micron Technology Inc v. Limestone Memory Systems LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Method for High-Speed Programming of a Nonvolatile Semiconductor Memory Device
  • Brief Description: The ’260 patent discloses a method to reduce the programming time for multilevel nonvolatile memory cells (e.g., Flash EEPROM). The method involves programming different groups of cells—destined for different final threshold voltage states—in parallel for a portion of the programming cycle to give cells requiring higher final voltages a "head start."

3. Grounds for Unpatentability

Ground 1: Obviousness over Fazio - Claims 1-4 are obvious over Fazio

  • Prior Art Relied Upon: Fazio (Patent 5,677,869)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Fazio taught all limitations of claims 1-4. Fazio discloses a method for programming multilevel flash memory cells at high speed using a concept of parallel programming with "strict ordering of states." In Fazio’s method, all cells destined for a higher state (e.g., State 2 or State 3) must first "pass through" the lower states. Specifically, Fazio teaches programming all cells destined for State 1 or higher to State 1 simultaneously (a first group and second group receiving a first programming voltage). Then, in a subsequent step, it programs all cells destined for State 2 or higher to State 2 (the second group receiving a second programming voltage). Petitioner asserted this directly maps to the ’260 patent's claimed method of consecutively applying a first programming voltage to a first and second group of cells, followed by applying a second programming voltage to the second group.
    • Dependent Claims: Petitioner contended Fazio also taught the limitations of dependent claims 2-4. For claim 2, Fazio explicitly teaches that the programming gate voltage increases for each successive state (V_G1 < V_G2 < V_G3), making the second programming voltage larger than the first. For claims 3 and 4, Fazio’s method extends to programming a third group of cells (to State 3) by applying the first and second programming voltages to that third group before applying a third, even larger programming voltage, thus providing the required "head start" steps.

Ground 2: Obviousness over Fazio in view of Terada - Claim 5 is obvious over Fazio in view of Terada

  • Prior Art Relied Upon: Fazio (Patent 5,677,869) and Terada (Patent 4,858,194)
  • Core Argument for this Ground:
    • Prior Art Mapping: Claim 5 depends from claim 1 and adds limitations specifying the physical connections for applying voltages: that programming voltages are applied to control gates via a word line, and select pulses are applied to the drains via corresponding bit lines. Petitioner argued that Fazio teaches the core programming method, including applying programming voltages to what it calls a "select gate," which a POSITA would understand to be a control gate connected to a word line. However, Fazio does not explicitly detail the connection of bit lines to cell drains. Terada was introduced to supply this conventional architectural detail. Terada describes a standard Flash memory architecture, presented as known prior art, where bit lines are connected to the drains of the memory cell transistors for programming.
    • Motivation to Combine: A POSITA would combine Fazio’s programming method with the conventional memory architecture described in Terada. Fazio teaches a generally applicable programming method, and Terada provides a well-known, compatible, and predictable architecture for its implementation. To practice Fazio’s method, which requires applying voltage to the cell drains, a POSITA would have naturally looked to a standard architecture like Terada’s that specifies how to make such connections using bit lines. The combination was presented as a simple application of a known programming technique to a known device architecture.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining Fazio's programming logic with Terada's standard hardware architecture would predictably result in a functional memory device. No technical hurdles were identified that would have discouraged this combination.

4. Key Claim Construction Positions

  • "programming voltage" (claims 1-5): Petitioner proposed this term be construed as "a voltage applied to a control gate of a memory cell." This construction was central to its arguments because the primary reference, Fazio, uses the term "select gate." Petitioner argued that based on Fazio’s disclosure and the knowledge of a POSITA, the "select gate" of Fazio is functionally and structurally equivalent to the "control gate" recited in the ’260 patent, and both are connected to a word line for receiving the programming voltage. This construction allows Fazio’s teachings on applying voltages to its "select gate" to be mapped directly onto the ’260 patent’s limitations.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-5 of the ’260 patent as unpatentable.