PTAB

IPR2016-00096

Micron Technology Inc v. Limestone Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Memory Device With Improved Flexible Redundancy Scheme
  • Brief Description: The ’181 patent discloses a semiconductor memory device architecture featuring memory arrays subdivided into multiple memory blocks. The technology purports to improve the efficiency of repairing defective memory cells by enabling spare memory cells located in one designated memory block to replace defective cells in other blocks within the same array.

3. Grounds for Unpatentability

Ground 1: Claims 1-2 and 6 are obvious over Sukegawa

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sukegawa discloses all limitations of independent claim 1. Specifically, Sukegawa teaches a DRAM device with memory arrays (quadrants) that are subdivided into memory blocks aligned vertically in the column direction. Petitioner asserted that Sukegawa’s "any to any" redundancy scheme—where spare memory rows in one block can be programmed to replace defective memory rows in any other block within the same quadrant—directly teaches the core concept of the ’181 patent. For dependent claim 2, Sukegawa’s array structure shows a plurality of second memory blocks arranged alternatively with the first. For dependent claim 6, the required column-aligned arrangement of normal and spare cells is inherent because they would share the same column/bit lines for efficient circuit layout.

Ground 2: Claim 3 is obvious over Sukegawa in view of Prince

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040), Prince (Betty Prince, Semiconductor Memories (2d ed. 1992))
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that claim 3, which depends from claim 2, adds the limitations of "a plurality of sense amplifier bands" that are "shared by adjacent memory blocks." The petition acknowledged that Sukegawa discloses sense amplifiers located between memory blocks but argued that the Prince textbook explicitly teaches the concept of sharing sense amplifiers between adjacent memory blocks. Prince describes this as part of an innovative divided bit-line architecture that enhances circuit density and performance.
    • Motivation to Combine: A primary objective of Sukegawa is to minimize chip size and reduce cost. Petitioner argued a POSITA would be motivated to consult a well-known resource like Prince to find established methods for furthering this objective. A POSITA would combine Prince's shared sense amplifier architecture with Sukegawa's device as a known design choice to improve layout density and reduce manufacturing costs.
    • Expectation of Success: Petitioner contended the combination would yield predictable results because shared sense amplifiers were a conventional and well-understood design choice in the field of semiconductor memory.

Ground 3: Claim 5 is obvious over Sukegawa in view of Walck

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040), Walck (Patent 4,967,397)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that claim 5, depending from claim 3, adds limitations requiring control circuitry for two distinct operational modes: driving a single memory block in a "normal operation mode" and simultaneously driving multiple memory blocks in a "particular operation mode." While Sukegawa shows a multi-array (quadrant) architecture, Walck was cited for its disclosure of a DRAM controller that enables these exact modes. Walck teaches that conventional DRAM operation involves accessing banks independently for read/write cycles (the "normal" mode) and accessing all banks simultaneously during refresh cycles (the "particular" mode).
    • Motivation to Combine: Petitioner argued that since all DRAM devices require a refreshing mechanism, a POSITA designing a multi-quadrant architecture like Sukegawa's would be motivated to implement a known refresh scheme. A POSITA would combine Walck's conventional, simultaneous-access refresh method with Sukegawa’s architecture to achieve faster and more efficient refreshing across all memory quadrants.
    • Expectation of Success: The combination was presented as the application of a standard refresh technique to a standard DRAM architecture, which would predictably result in an effectively refreshed memory device.

Ground 4: Claim 7 is obvious over Sukegawa in view of Oh

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040), Oh (Patent 5,355,339)

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that claim 7, which depends from claim 1, adds the negative limitation that memory blocks other than the one containing spare cells have no spare cells. Sukegawa teaches that spare memory may exist in each, or at least some, blocks. Oh was introduced to teach the specific claimed configuration, as Oh explicitly discloses a redundancy architecture where spare word lines are consolidated into a single memory array, while other arrays contain no spare lines, for the stated purpose of maximizing repair efficiency and optimizing chip area.
    • Motivation to Combine: Both Sukegawa and Oh address the common problem of repairing defective memory while minimizing the required chip space. Petitioner argued a POSITA would therefore be motivated to combine their teachings. Modifying Sukegawa's redundancy scheme to adopt Oh's more area-efficient strategy of consolidating all spare cells into one block would have been an obvious design choice.
    • Expectation of Success: The result of applying Oh's redundancy placement strategy to Sukegawa's multi-block architecture was argued to be predictable and would achieve the known benefits described in Oh.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 4 over Sukegawa in view of Prince, arguing Prince’s teaching of sharing column decoders between memory blocks rendered the claim obvious for the same reasons of cost and space reduction cited for sharing sense amplifiers.

4. Key Claim Construction Positions

  • "word lines" (claims 1-7): Petitioner proposed this term be construed as "conductive materials that run horizontally through a memory device that connect memory cells in a physical row." This construction was based on the common understanding in the art and supported by technical literature.
  • "spare memory cells" (claims 1-7): Petitioner proposed this term be construed as "memory cells capable of replacing defective memory cells." This construction was based on the term’s plain meaning and its description within the ’181 patent’s specification.
  • "sense amplifier bands" (claims 3, 5): Petitioner proposed this term be construed as "amplifiers along the horizontal direction that sense the contents of memory cells and restore (amplify) them to full levels." This construction was derived from the function and arrangement of sense amplifiers described in the ’181 patent and general knowledge in the art.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-7 of the ’181 patent as unpatentable.