PTAB

IPR2016-00114

MSI Computer Corp v. Kinglite Holdings Inc

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1. Case Identification

2. Patent Overview

  • Title: Multitasking Microcontroller
  • Brief Description: The ’200 patent discloses adapting a standard microcontroller, such as a keyboard controller, to handle multitasking. The invention utilizes firmware to manage a first set of higher-priority functions and a second set of lower-priority functions through prioritization and time-sharing schemes.

3. Grounds for Unpatentability

Ground 1: Obviousness over ST20 RTOS and Intel 8051 Controller - Claims 19 and 21-23 are obvious over ST20 RTOS in view of Intel 8051 Controller.

  • Prior Art Relied Upon: ST20 RTOS (a 1996 technical document describing a real-time operating system kernel) and Intel 8051 Controller (a 1995 technical manual for a commercial microcontroller).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the Intel 8051 Controller is a commercially available microcontroller designed for keyboard control, analogous to the “device” in the ’200 patent. The ST20 RTOS document teaches the core software functionality recited in claim 19: a “multi-priority preemptive scheduler” that maintains separate high-priority and low-priority process queues. ST20 RTOS disclosed running high-priority tasks to completion while using a time-slicing scheme for low-priority tasks. This time-slicing involves using a timer, aborting (or “descheduling”) a low-priority task if its time slice expires, and saving its state (the instruction pointer, or Iptr) in memory to be resumed later. This combination allegedly taught all limitations of independent claim 19. Dependent claims 21-23 were allegedly obvious as they recited inherent features of using the Intel 8051 Controller (interfacing with BIOS, having dual interfaces for keyboard and power management) with keyboard functions naturally having higher priority.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because the industry recognized a need to handle multiple functions (e.g., keyboard control and power management) within a single device. The Intel 8051 Controller, with its expanded memory, was designed to be adapted for such complex functionality. A POSITA would find it obvious to implement a known multitasking solution, such as an RTOS kernel described in ST20 RTOS, on this capable hardware to achieve the desired multitasking.
    • Expectation of Success: A POSITA would have a high expectation of success because RTOS kernels were designed to be implemented on microcontrollers, and the Intel 8051 was specifically designed to be adapted with new software functionality.

Ground 2: Obviousness over ST20 RTOS, Intel 8051 Controller, and IBM PS/2 - Claims 9 and 20 are obvious over ST20 RTOS in view of Intel 8051 Controller and IBM PS/2.

  • Prior Art Relied Upon: ST20 RTOS, Intel 8051 Controller, and IBM PS/2 (a 1988 technical reference describing keyboard controller commands).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 by adding the IBM PS/2 reference to teach specific command types. Petitioner asserted that IBM PS/2 disclosed a low-priority "A5" command (Long Password) that is necessarily executed in burst mode, which directly taught the "burst enable function" limitation of claim 20. The combination of ST20 RTOS and Intel 8051 Controller provided the multitasking framework (as argued in Ground 1), and IBM PS/2 provided a specific example of a low-priority function that would be managed by this framework. The method steps of claim 9 were mapped to the prior art in a manner similar to the device limitations of claim 19.
    • Motivation to Combine: A POSITA building the multitasking controller of Ground 1 would be motivated to incorporate support for standardized, widely adopted host-controller commands, such as those detailed in IBM PS/2, to ensure system compatibility and functionality. As the A5 command was a known low-priority, burst-mode command, it would have been an obvious candidate for management by the low-priority task queue of the ST20 RTOS.
    • Expectation of Success: Integrating a standard command protocol into a multitasking microcontroller was argued to be a predictable design choice with a high expectation of success.

Ground 3: Anticipation by Kuki - Claims 19 and 21 are anticipated by Kuki.

  • Prior Art Relied Upon: Kuki (Patent 5,168,566).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Kuki disclosed each and every limitation of claims 19 and 21. Kuki taught a peripheral multi-task control device that offloads scheduling functionality from a host computer. The device explicitly managed tasks using both priority-based execution and a time-sharing process. Kuki disclosed using a timer to generate interrupts for the time-sharing process, executing high-priority tasks immediately while voiding the time-sharing process, aborting a lower-priority task when its designated time is up, storing the task’s context (as “old stack pointer data”), and resuming the aborted task upon receiving a “next command.” For claim 21, Kuki's disclosure of a peripheral device that handles interrupts and performs system initialization was argued to inherently require interfacing with the host system's BIOS firmware and operating system.

4. Key Claim Construction Positions

  • Petitioner argued that the preamble of claim 19, which recites "a device for handling a first set of higher-priority functions and a second set of lower-priority functions," has patentable weight as it is essential to understanding the limitations in the claim body.
  • “a device”: Construed as a "hardware component," consistent with the patent’s goal of adapting a physical microcontroller with multitasking software.
  • “start a timer...abort the function...”: This sequence of operations in claim 19 should be construed to mean "time sharing."
  • “data return vector”: Construed as an "area of memory that stores, at least, an address of a point of abortion," based on the specification's reference to a "data return vector register."

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 9 and 19-23 of Patent 5,937,200 as unpatentable.