PTAB

IPR2016-00324

Micron Technology Inc v. Innovative Memory Systems Inc

Key Events

Petition

petition

Title: NAND Flash Memory Controller Exporting a NAND Interface
Brief Description: The ’212 patent discloses a standalone flash memory controller for interfacing between a host device and a NAND flash memory. The controller's allegedly novel feature is its use of a NAND interface on the host-facing side, which purportedly allows for easier integration and upgrades in systems where the host expects to communicate directly with a NAND device.

Prior Art Relied Upon: Sakaue (Patent 7,516,371).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Sakaue discloses all limitations of independent claim 1. Sakaue teaches an Error Check and Correct (ECC) controller that interfaces between a host and a NAND flash memory module. This controller includes electronic circuitry, a first interface to the memory, a second interface to the host (which Petitioner asserted is a NAND interface), an error correction module (Sakaue’s data-path/ECC circuit), and an additional functionality module (Sakaue's various other control circuits). Petitioner contended that fabricating the controller on a die distinct from the flash memory die, as claimed, was an obvious and common design choice for integrated circuits to improve performance and reduce footprint.
- Motivation to Combine (for §103 grounds): Not applicable for this single-reference ground. The arguments were based on Sakaue’s express teachings combined with the knowledge of a person of ordinary skill in the art (POSITA).

Prior Art Relied Upon: Sakaue (Patent 7,516,371) and Sakui (Patent 6,594,169).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Sakaue discloses all elements of the base claims (4 and 10), but does not explicitly teach packaging the controller and flash memory device in a "common packaging." Sakui was introduced to supply this missing element, as it teaches packaging a NAND flash memory chip and its associated peripheral circuitry (including an ECC circuit) together in a single multi-chip package (MCP) to improve integration density and performance.
- Motivation to Combine (for §103 grounds): A POSITA would combine these references because both were assigned to Toshiba and addressed NAND memory systems. As Sakaue was silent on packaging, a POSITA would look to known techniques like that in Sakui to implement Sakaue’s system. The combination was presented as a simple design choice to achieve the known benefits of MCPs, such as increased density and operational speed.
- Expectation of Success (for §103 grounds): A POSITA would expect that applying Sakui’s well-known packaging technique to Sakaue’s memory system would predictably result in a more compact and efficient device.

Prior Art Relied Upon: Sakaue (Patent 7,516,371) and Vainsencher (Application # 2004/0117688).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Sakaue teaches the core method steps of writing and reading data between a host and NAND memory via a controller, including generating generic ECC codes. However, Sakaue does not explicitly disclose that these codes are "parity bits." Vainsencher was introduced to teach the use of an ECC processor that specifically "generates either parity or syndrome bits" for error correction when writing data to a NAND flash device.
- Motivation to Combine (for §103 grounds): A POSITA would combine the teachings because both references address the same problem of error correction in NAND memory systems using an external controller. Implementing the specific parity bit generation from Vainsencher into the more general ECC framework of Sakaue was argued to be an obvious design choice, representing a simple substitution of one known error correction scheme for another to achieve predictable results.
- Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in using Vainsencher's parity bit scheme within Sakaue's controller architecture to achieve effective error detection and correction.

"additional functionality module" / "error correction module": Petitioner argued these terms are nonce words that fail to recite sufficient structure and should be construed as means-plus-function limitations under 35 U.S.C. §112, ¶ 6. The corresponding structure was identified in the specification as generic "hardware, software, firmware, or any combination thereof." This construction was central to mapping these functional limitations to corresponding circuits in the prior art.
"NAND interface" / "NAND interface protocol": Petitioner proposed these terms be construed to mean "any interface protocol that uses sequences of transferred bytes and uses control signals equivalent in functionality to CLE, ALE, CE, WE, and RE signals," based on an explicit definition in the ’212 patent's specification. This construction was key to arguing that the host-side interfaces in the prior art met the claim limitations.
"deploying": Petitioner argued that in the context of claims 10 and 15, "deploying" should be construed to mean "connecting," as the controller must be physically connected to the memory or host to be operative.

Petitioner requested institution of an inter partes review and cancellation of claims 1, 2, 4, 5, 9, 10, 11, 15, 16, and 17 of the ’212 patent as unpatentable.