PTAB

IPR2016-00327

Micron Technology Inc v. Innovative Memory Systems Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Highly Compact Non-Volatile Memory and Method Therefor with Internal Serial Buses
  • Brief Description: The ’159 patent describes a non-volatile semiconductor memory architecture designed to reduce redundancy and improve performance in read/write circuits. The system redistributes modules into parallel-operating "core" portions and a smaller set of serial-processing "common" portions, which communicate via an internal serial bus controlled by a bus controller.

3. Grounds for Unpatentability

Ground 1: Anticipation over Kawamura - Claims 1, 5, 11, and 12 are unpatentable under 35 U.S.C. §102(b) as anticipated by Kawamura.

  • Prior Art Relied Upon: Kawamura (Patent 6,288,936).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kawamura, which describes a non-volatile flash memory for storing multivalue data, discloses every limitation of the challenged claims. Independent claim 1 recites a memory device with an array of memory cells, a set of read/write circuits operating in parallel, a bus, and a bus controller. Petitioner asserted that Kawamura’s NAND flash memory device meets these limitations. Specifically, Kawamura's page buffers, input-output buffer (IOB), and program input circuit collectively form the claimed "set of read/write circuits." Petitioner argued these circuits operate in parallel to read from or write to memory cells, as Kawamura explicitly states that data in all columns can be read to the page buffer at once and that memory cells can be programmed simultaneously.
    • Prior Art Mapping (cont.): The read/write circuits were argued to form a "component group." The connections between Kawamura's page buffers and the IOB, used for transferring data, were identified as the claimed "bus." The combination of Kawamura’s Main Controller, Page Buffer Controller, and various control signals (e.g., YD1 selection signals) that manage data flow and operations on this bus were asserted to be the claimed "bus controller."
    • Prior Art Mapping (Dependent & Other Claims): For claim 5, which includes a "means for controlling operations" limitation, Petitioner mapped the recited function to the structure of Kawamura’s controllers and control lines, arguing they are structurally equivalent to the corresponding structure disclosed in the ’159 patent. For dependent claims 11 and 12, Petitioner pointed to Kawamura’s disclosure of memory cells that can store a single bit of data (for claim 11) as well as cells that can store multiple bits of data (for claim 12).

4. Key Claim Construction Positions

  • "bus" (claims 1, 5, 11, 12): Petitioner proposed that under the broadest reasonable interpretation, "bus" should be construed as a "connection that allows communications between components." This construction was argued to be consistent with the ’159 patent’s description of serial and data buses and supported by industry dictionary definitions. This broad construction allowed Petitioner to map the term onto the various signal and data pathways shown in Kawamura.
  • "means for controlling operations of components among each component group with its bus" (claim 5): Petitioner identified this as a means-plus-function term under pre-AIA 35 U.S.C. §112, ¶ 6.
    • Function: "controlling operations of components among each component group with its bus."
    • Corresponding Structure in the ’159 patent: Petitioner asserted the corresponding structure is the "Stack Bus Controller 430 and Control Lines 411-k, and equivalents thereof." This construction was central to Petitioner's argument that the controllers disclosed in Kawamura were structurally equivalent and performed the identical function.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 5, 11, and 12 of the ’159 patent as unpatentable.