PTAB

IPR2016-00330

Micron Technology Inc v. Innovative Memory Systems Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Zone Boundary Adjustment for Defects in Non-Volatile Memories
  • Brief Description: The ’498 patent discloses techniques for managing defects in non-volatile memories, such as flash memory. The system organizes memory blocks into adjustable "logical zones" and uses a controller to dynamically reassign blocks to different zones to compensate for defective blocks, thereby improving yield and extending the device’s usable lifetime.

3. Grounds for Unpatentability

Ground 1: Obviousness over Tanaka and Estakhri - Claims 1, 2, 11, 12, 21, 27, 32, 38, 43, and 44 are obvious over Tanaka in view of Estakhri.

  • Prior Art Relied Upon: Tanaka (European Patent No. EP 0,896,280 A2) and Estakhri (Patent 6,034,897).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Tanaka taught the core elements of the independent claims. Tanaka disclosed a non-volatile memory system with a controller that organizes memory into a plurality of "logical zones" for address translation. Critically, Tanaka described a "zone division control" scheme where the controller adjusts the correspondence of blocks to zones by replacing defective blocks with redundant blocks to ensure each zone has a sufficient number of effective blocks. This adjustment could happen dynamically in response to "acquired defective blocks" that occur during normal use. Petitioner contended that Estakhri, which disclosed a single controller performing memory operations, address translation, and defective block management, rendered it obvious that the same controller disclosed in Tanaka would perform all the functions required by the claims, including adjusting the block-to-zone correspondence.
    • Motivation to Combine: Petitioner asserted that a Person of Ordinary Skill in the Art (POSITA) would combine Tanaka and Estakhri because they are in the same field of flash memory control, address common issues of defect management and logical block grouping, and Estakhri is explicitly described as for use in a system like Tanaka's. The combination would have been a simple substitution of a known type of controller (Estakhri's) into a known system (Tanaka's) to achieve predictable results.
    • Expectation of Success: A POSITA would have a high expectation of success, as combining the controller functions of Estakhri with the memory management system of Tanaka involved applying known techniques to improve a similar device in a predictable manner.

Ground 2: Obviousness over Tanaka, Estakhri, and Mukaida - Claims 5, 6, 15, 16, 47, and 48 are obvious over Tanaka in view of Estakhri and Mukaida.

  • Prior Art Relied Upon: Tanaka (EP 0,896,280 A2), Estakhri (Patent 6,034,897), and Mukaida (Patent 7,020,739).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address dependent claims requiring memory comprised of a "plurality of planes" where zones are comprised of blocks from multiple planes. Petitioner argued that the base combination of Tanaka and Estakhri taught the underlying system of adjustable logical zones. Mukaida was added because it explicitly taught dividing physical blocks into multiple planes (which it calls "groups" or "banks") and forming logical zones (which it calls "virtual blocks") that are comprised of blocks from different planes. Mukaida further disclosed that these planes could be on a single chip or span multiple chips, thereby teaching the limitations of claims requiring planes from "more than one chip."
    • Motivation to Combine: A POSITA would combine Mukaida's teachings with the Tanaka/Estakhri system because all three references address controlling flash memory and creating logical block groups. Mukaida and Estakhri both disclosed using planes to facilitate parallel operations, providing a clear motivation to incorporate Mukaida's multi-plane zone structure to increase the speed and performance of the base system.
    • Expectation of Success: The combination was a predictable integration of known memory architecture (planes) with a known management system to enhance performance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including:

    • Claims 5, 6, 15-16, and 47-48 are obvious over Tanaka, Estakhri, and Hazen (Patent 6,088,264), where Hazen was cited for its teaching of partitioning a single memory device into planes for simultaneous operations.
    • Claims 22 and 33 are obvious over Tanaka, Estakhri, and Garvin (Patent 6,260,156), where Garvin was cited for its teaching of using a "stress test" to identify defective memory blocks, allegedly rendering obvious the claim limitation of "testing said memory blocks."

4. Key Claim Construction Positions

  • "logical zone": Petitioner proposed this term be construed as "a logical subdivision of the total capacity of the non-volatile memory die." This construction was based on an explicit definition in the ’498 patent specification and was central to applying Tanaka, which used terms like "logical areas" and "zones" for the same purpose.
  • "plane": Petitioner proposed construing this term as a "physical subdivision of the memory on a single die," based on its express definition in the ’498 patent. This construction was important for the arguments in Grounds 2 and 3, which relied on prior art that partitioned memory dies into physical subdivisions to enable parallel operations.
  • "multi-state storage units": Petitioner argued this term means "storage elements that store two or more bits of data per storage element," consistent with the patent's specification. This was relevant for claims 2, 12, and 44.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and cancellation of claims 1, 2, 5, 6, 11, 12, 15, 16, 21, 22, 27, 32, 33, 38, 43, 44, 47, and 48 of the ’498 patent as unpatentable.