PTAB

IPR2016-00386

SK Hynix Inc v. Elm 3DS Innovations LLC

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Key Events
Petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’672 patent discloses methods for fabricating three-dimensional (3D) stacked integrated circuits (ICs). The technology involves thinning semiconductor substrates to a thickness that renders them "substantially flexible," bonding multiple thinned substrates, and forming vertical interconnections (through-silicon vias) to create a high-density device. The patent also describes using low tensile stress dielectrics to manage mechanical stress in the stacked structure.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bertin, Poole, and Leedy ’695 - Claims 17, 18, 22, 84, 95, 129-132, 145, 146, and 152 are obvious over Bertin in view of Poole and Leedy ’695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin discloses the foundational technology: a 3D multichip package with densely stacked semiconductor chips, vertical interconnects, and substrates thinned to 20 micrometers or less. However, Bertin used a conventional wet etching process for thinning and did not explicitly teach polishing the thinned substrate or using a low-stress dielectric. Poole was introduced to supply the missing polishing step, as it teaches a well-known two-step grinding and chemical mechanical polishing (CMP) process to thin substrates to 10 micrometers, resulting in a planar surface with minimal damage. Leedy ’695 was introduced to teach the use of low tensile stress dielectrics (e.g., silicon dioxide or silicon nitride) to improve structural integrity and surface flatness, which are critical for reliable stacked ICs.
    • Motivation to Combine: A POSITA would combine these references to improve upon Bertin's design. The motivation to combine Bertin with Poole was to replace Bertin’s wet etching with Poole’s more advanced grinding and polishing process, a simple substitution of one known thinning method for another to achieve a superior, smoother surface required for reliable bonding and interconnect formation in a 3D stack. A POSITA would combine this result with Leedy ’695 to address the well-known problem of mechanical stress in thin films. Leedy ’695 explicitly teaches that its low-stress dielectrics increase structural integrity and are advantageously used to insulate circuit devices and interconnects, providing a clear solution to a known issue in the field.
    • Expectation of Success: A POSITA would have a high expectation of success because the combination involved applying well-understood, predictable processes. Poole’s CMP process was a standard technique for achieving smooth, thin substrates. Leedy ’695’s plasma-enhanced chemical vapor deposition (PECVD) for low-stress dielectrics was a common, versatile process compatible with standard IC fabrication, predictably resulting in a stacked IC with lower overall stress.

Ground 2: Obviousness over Yu and Leedy ’695 - All challenged claims are obvious over Yu in view of Leedy ’695.

  • Prior Art Relied Upon: Yu (a 1996 IEEE conference paper titled "Real-Time Microvision System with Three-Dimensional Integration Structure") and Leedy ’695 (Patent 5,354,695).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Yu discloses a 3D integrated structure made by vertically stacking 2D large-scale integration (LSI) wafers. Critically, Yu teaches thinning the wafers to 30 µm by a "Grinding and Polishing" step, directly teaching the core limitation of a "substantially flexible" substrate as construed by Petitioner. Yu further discloses the stacked relationship, interconnects, and use of a silicon dioxide (SiO₂) dielectric. Yu, however, does not explicitly disclose that its dielectric has the low tensile stress recited in the claims.
    • Motivation to Combine: A POSITA would combine Yu with Leedy ’695 to improve the reliability of Yu’s 3D structure. The motivation was to substitute the standard dielectric in Yu with the low-stress dielectric taught by Leedy ’695. This substitution would reduce the probability of cracking and warpage caused by stress, particularly around the through-vias, which was a known failure point in 3D ICs. Both references address the same technical problem of vertically integrating IC devices.
    • Expectation of Success: A POSITA would reasonably expect success because Leedy ’695’s fabrication techniques for low-stress films were compatible with established IC processing methods. Applying Leedy ’695’s known deposition recipes and common tools to the stacked structure in Yu was a straightforward application of a known technique to a known device to achieve a predictable improvement in stress management and device reliability.

  • Additional Grounds: Petitioner asserted that claims 143, 144, and 151 are obvious over Bertin and Poole alone. Petitioner also asserted an alternative ground that all challenged claims are obvious over Yu in view of Kowa (Japanese Patent Publication H3-151637), which teaches stress management through stress balancing rather than inherently low-stress materials.

4. Key Claim Construction Positions

  • "substantially flexible semiconductor [] substrate": Petitioner argued this term required a specific construction based on the patentee’s role as its own lexicographer in the specification and arguments made during prosecution of a related patent. The proposed construction is “a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed.” This construction was central to the invalidity arguments, as it provided a clear, objective standard for a term of degree that Petitioner argued was met by the prior art’s disclosure of thinning and polishing wafers to thicknesses well below 50 µm.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 17, 18, 22, 84, 95, 129-132, 143-146, 151, and 152 of the ’672 patent as unpatentable.