PTAB

IPR2016-00387

SK Hynix Inc v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’778 patent describes fabrication methods for three-dimensional (3D) integrated circuits (ICs). The methods involve thinning semiconductor substrates to make them "substantially flexible," bonding multiple thinned substrates into a vertical stack, and forming vertical through-silicon via (TSV) interconnections. A key aspect is the use of low tensile stress dielectric materials to manage mechanical stress, which is critical for maintaining structural integrity and yield in the thinned, stacked layers.

3. Grounds for Unpatentability

Ground 1: Obviousness over Bertin and Leedy - Claims 1 and 14 are obvious over Bertin in view of Leedy '695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754) and Leedy '695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin taught the core elements of the challenged independent claims, including a 3D multichip package with stacked semiconductor chips, monocrystalline substrates, and vertical interconnect conductors passing through the substrates. Bertin also disclosed silicon-based dielectric insulators (oxidized sidewalls of trenches) for the interconnects. However, Bertin did not explicitly disclose that these dielectrics have a low tensile stress of less than 5×10⁸ dynes/cm². Leedy '695, which is incorporated by reference into the ’778 patent, explicitly taught the fabrication of flexible ICs using very thin, low-stress dielectric materials (e.g., silicon dioxide) with tensile stress below this claimed threshold.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine the teachings because both references aimed to improve high-density 3D ICs. A POSITA would have recognized that the high stress inherent in the dielectrics of a structure like Bertin’s would be a source of manufacturing and reliability problems. Leedy '695 provided an express solution by teaching that low tensile stress dielectrics improve "surface flatness and membrane structural integrity," which are critical for subsequent fabrication steps and durability in thinned structures.
    • Expectation of Success: A POSITA would have a reasonable expectation of success in substituting Leedy’s low-stress dielectric material for the dielectrics in Bertin. Leedy '695 described its materials as versatile and compatible with well-known deposition techniques like plasma-enhanced chemical vapor deposition (PECVD), providing a predictable path to achieving a more robust version of Bertin’s stacked IC.

Ground 2: Obviousness over Bertin, Leedy, and Poole - Claims 2, 8, 31, 32, 44, 46, and 52-54 are obvious over Bertin and Leedy '695, further in view of Poole.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Leedy '695 (Patent 5,354,695), and Poole (Patent 5,162,251).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 1 and added Poole to address limitations in dependent claims related to a "substantially flexible" substrate. Petitioner contended this term requires the substrate to be thinned to less than 50 µm and subsequently polished. While Bertin taught thinning substrates to 20 µm or less via wet etching, it did not explicitly disclose a polishing step. Poole taught a two-step thinning process for semiconductor substrates that involved first grinding and then chemical mechanical polishing (CMP) to achieve a final thickness of 10 µm with a surface "almost totally free of work damage."
    • Motivation to Combine: A POSITA would have been motivated to replace Bertin’s wet etching process with Poole’s well-known grinding and polishing technique. This substitution would predictably result in a thinner, more planar, and less-damaged substrate surface, which is highly desirable for facilitating reliable bonding and forming vertical interconnects in a 3D stack. The motivation was to use a superior, well-known thinning method to achieve a predictable improvement in device quality.
    • Expectation of Success: Success was predictable because Poole's method was a simple substitution of one well-known primary method for thinning substrates for another.

Ground 3: Obviousness over Hsu and Leedy - Claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 are obvious over Hsu in view of Leedy '695.

  • Prior Art Relied Upon: Hsu (Patent 5,627,106) and Leedy '695 (Patent 5,354,695).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground presented Hsu as an alternative primary reference to Bertin. Petitioner argued Hsu disclosed all features of the independent claims except for the low-stress dielectric. Hsu taught a method of creating 3D stacked ICs by grinding and polishing a substrate to a thickness of less than 10 µm, forming vertical interconnects, and using a silicon dioxide dielectric film. Petitioner asserted that Hsu provided a stronger basis than Bertin for the thinning and polishing limitations. As with Ground 1, the combination with Leedy '695 was necessary to supply the teaching of a low tensile stress dielectric.
    • Motivation to Combine: The motivation to combine Hsu and Leedy '695 was the same as in Ground 1: a POSITA would seek to improve the structural integrity of Hsu's thinned, stacked structure by incorporating the known stress-management solution taught by Leedy '695.
    • Expectation of Success: A POSITA would expect success for the same reasons as in Ground 1, as Leedy's low-stress dielectrics were taught to be compatible with conventional IC fabrication processes like those described in Hsu.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including Ground 4 (Hsu in view of Kowa) to address alternative claim constructions related to stress balancing, and Ground 5 (Bertin in view of Leedy '695) under alternative constructions of "substantially flexible" that do not require polishing.

4. Key Claim Construction Positions

  • "semiconductor substrate" is "substantially flexible": Petitioner argued that the Patent Owner acted as its own lexicographer, defining this phrase to mean "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on explicit statements in the ’778 patent specification and arguments made during the prosecution of related patents to overcome indefiniteness rejections.
  • "substantially flexible circuit layer": Petitioner argued for a two-part construction where this term means a circuit layer (1) having a semiconductor substrate thinned to less than 50 µm and subsequently polished, and (2) where the dielectric material used in processing has a tensile stress of 5×10⁸ dynes/cm² or less. This construction was also based on the intrinsic record, including the specification and prosecution history where the patentee defined the term to require both thinness and low dielectric stress.

5. Relief Requested

  • Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1, 2, 8, 14, 31, 32, 44, 46, and 52-54 of Patent 8,841,778 as unpatentable.