Samsung Electronics Co Ltd v. Elm 3DS Innovations LLC

1. Case Identification

• Case #: IPR2016-00388
• Patent #: 7,193,239
• Filed: December 28, 2015
• Petitioner(s): Samsung Electronics Co., Ltd.; Micron Technology, Inc.; and SK Hynix Inc.
• Patent Owner(s): ELM 3DS Innovations, LLC
• Challenged Claims: 1, 10-13, 18-20, 60-63, 67, 70-73, and 77

2. Patent Overview

• Title: Stacked Integrated Circuit Memory
• Brief Description: The ’239 patent discloses methods for fabricating three-dimensional (3D) integrated circuits (ICs) by stacking multiple monolithic substrates. The technology involves thinning substrates to make them "substantially flexible," bonding them into layers, and creating vertical interconnections through the substrates.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yu and Leedy – Claims 1, 10-13, 18-20, 60-63, 67, 70-73, and 77 are obvious over Yu in view of Leedy ’695.

• Prior Art Relied Upon: Yu ("Real-Time Microvision System with Three-Dimensional Integration Structure," a 1996 IEEE publication) and Leedy ’695 (Patent 5,354,695).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Yu disclosed the core structural elements of the challenged claims, including a 3D IC fabricated by stacking multiple thinned and polished silicon wafers. Yu explicitly taught thinning substrates to approximately 30µm—well below the 50µm threshold for "substantially flexible" as construed by Petitioner—and stacking them using an adhesive bonding layer and vertical interconnects (micro-bumps). Petitioner contended Yu taught every limitation of independent claims 1, 13, 60, and 70 except for the use of a "low stress dielectric." This missing element, Petitioner asserted, was supplied by Leedy ’695. Leedy ’695 taught the fabrication of flexible ICs using very thin, low-stress dielectric materials (e.g., silicon dioxide) deposited with a specific tensile stress of less than 8×10⁸ dynes/cm², which aligned with the stress limitations recited in several dependent claims.
  • Motivation to Combine: Petitioner asserted several motivations for a person of ordinary skill in the art (POSITA) to combine the teachings of Yu and Leedy ’695. First, applying Leedy’s low tensile stress dielectric to Yu’s stacked structure would improve structural integrity and reliability, allowing the device to better withstand the high temperatures of IC processing without cracking or warpage. Second, the conformal chemical vapor deposition (CVD) process taught in Leedy ’695 was inherently lower-stress and well-suited for coating the through-vias of Yu’s design. Third, both references addressed the same technical problem of vertically integrating IC devices, making the combination a predictable substitution of one known element (Leedy’s low-stress dielectric) for another (Yu’s conventional dielectric) to achieve a known benefit.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in the combination because Leedy ’695 disclosed fabrication techniques and deposition recipes compatible with established IC processing methods like those used in Yu. The combination involved applying a known material using a known process to a known structure to achieve a predictable improvement in stress management.

4. Key Claim Construction Positions

• "a substantially flexible" semiconductor substrate (claims 1, 13): Petitioner proposed this term should be construed to mean "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." Petitioner argued the patentee acted as its own lexicographer by explicitly defining the term in the specification. This construction was further supported by arguments the patentee made during the prosecution of related patents to overcome indefiniteness rejections, thereby creating prosecution history estoppel.
• "die is substantially flexible" / "dice are substantially flexible" (claims 60, 70): Petitioner proposed a more detailed construction for this term: "an integrated circuit having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction incorporated both the thinning requirement from the specification and an additional low-stress dielectric requirement that the patentee relied upon to distinguish prior art during the prosecution of related applications.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that institution was appropriate and that the petition was not redundant with a concurrently filed petition (IPR2016-00393) against the same patent. Petitioner asserted that the two petitions relied on different primary references (Yu vs. Bertin in the other petition) that provided stronger disclosures for different claim elements. Furthermore, the references qualified as prior art under different statutory sections (Yu under 35 U.S.C. §102(a) and Bertin under §102(b)), providing distinct bases for unpatentability.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1, 10-13, 18-20, 60-63, 67, 70-73, and 77 of the ’239 patent as unpatentable.