PTAB

IPR2016-00391

Micron Technology Inc v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’862 patent discloses methods for fabricating three-dimensional (3D) stacked integrated circuits. The technology involves thinning semiconductor substrates to below 50 µm to make them "substantially flexible," bonding these thinned substrates into a vertical stack, and forming vertical interconnections through the substrates to connect the layers. The patent also describes using low tensile stress dielectric materials to manage mechanical stress within the stacked structure.

3. Grounds for Unpatentability

Ground 1: Claims 30, 34, 36, 135-138, and 147 are obvious over Bertin, Poole, and Leedy ’695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin discloses the foundational technology: a 3D multichip package with densely stacked semiconductor chips, thinned substrates (to 20 µm or less), and vertical interconnections passing through the substrates. However, Bertin thins substrates using wet etching and does not explicitly disclose polishing or the use of low-stress dielectrics. To address these limitations, Petitioner asserted that Poole teaches a well-known two-step grinding and chemical mechanical polishing (CMP) process to thin substrates to 10 µm, resulting in a smooth, planar surface. Further, Leedy ’695, which is incorporated by reference in the ’862 patent, explicitly teaches the fabrication of integrated circuits using low tensile stress dielectric materials (e.g., silicon dioxide) to increase structural integrity.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSA) would combine these references to improve upon Bertin’s design. A POSA would replace Bertin’s wet etching process with Poole’s well-known grinding and polishing process to achieve a simpler manufacturing flow and a superior, planar surface, which is desirable for reliable bonding and interconnection. A POSA would also incorporate the low-stress dielectrics of Leedy ’695 into Bertin’s structure to improve the structural integrity and durability of the 3D stack, a known concern in the field.
    • Expectation of Success: Petitioner contended a POSA would have a reasonable expectation of success. Combining Bertin and Poole was a simple substitution of one known thinning technique for another to achieve the predictable result of a thin, smooth substrate. Similarly, incorporating Leedy ’695’s versatile, low-stress dielectrics using standard deposition techniques like PECVD would predictably result in a more reliable stacked structure with lower overall stress.

Ground 2: Claims 30, 34, 36, 135-138, and 147 are obvious over Hsu and Leedy ’695.

  • Prior Art Relied Upon: Hsu (Patent 5,627,106) and Leedy ’695 (Patent 5,354,695).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Hsu discloses a method of connecting 3D stacked memory chips (e.g., SRAM), including a master chip and subordinate chips. Hsu teaches thinning the subordinate chip substrate to approximately 10 µm by grinding and polishing its bottom surface. It also discloses forming vertical interconnections through the thinned substrate. Like Bertin, Hsu does not explicitly disclose that its dielectric layers (e.g., silicon dioxide films) are characterized by low stress. Leedy ’695 was cited to supply this missing element, as it describes fabricating circuits with very thin, low-stress dielectric materials to improve durability.
    • Motivation to Combine: A POSA would combine Hsu and Leedy ’695 because both references are directed toward improving high-density 3D integrated circuits. A POSA would have been motivated to apply the known stress-reduction techniques from Leedy ’695 to the 3D stacked structure in Hsu to improve device reliability and manufacturability. This combination represents using a known technique (low-stress dielectrics) to improve a similar device (a 3D IC stack) in a predictable way.
    • Expectation of Success: A POSA would expect success in this combination. Leedy ’695 teaches that its low-stress dielectrics are versatile and compatible with a wide range of IC processing techniques and temperatures. Therefore, substituting Leedy ’695’s low-stress dielectric deposition process for the conventional process used in Hsu would predictably yield a more robust 3D memory device.

  • Additional Grounds: Petitioner asserted alternative obviousness grounds in case the Board adopted different claim constructions. These included Hsu in view of Kowa (Japanese Patent Pub. H3-151637) for stress balancing, and Bertin in view of Leedy ’695 alone for claims not requiring polishing.

4. Key Claim Construction Positions

Petitioner argued that the patentee acted as his own lexicographer, defining key terms in the specification and during prosecution of related applications.

  • "substantially flexible … semiconductor substrate": Petitioner proposed the construction: "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on explicit definitions provided in the ’862 patent specification and unambiguous statements made by the applicant during prosecution to overcome indefiniteness rejections.
  • "substantially flexible circuit layer" / "integrated circuit layer": Petitioner proposed the construction: "a circuit layer having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction was based on arguments made during prosecution that distinguished a flexible circuit layer from a flexible substrate, asserting that the layer required both thinness and the use of low-stress dielectrics.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 30, 34, 36, 135-138, and 147 of the ’862 patent as unpatentable.