PTAB

IPR2016-00393

Samsung Electronics Co Ltd v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’239 patent discloses three-dimensional integrated circuits (3D ICs) and methods for their fabrication. The technology involves stacking multiple thinned monolithic substrates, bonding them into layers, and forming vertical interconnections, with a focus on managing mechanical stress through techniques like using low tensile stress dielectrics.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 13 are obvious over Bertin ’754 and Poole.

  • Prior Art Relied Upon: Bertin ’754 (Patent 5,202,754) and Poole (Patent 5,162,251).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bertin ’754 disclosed the foundational elements of the challenged claims, including a 3D multichip package with densely stacked semiconductor chips thinned to 20 µm or less. However, Bertin ’754 used a wet etching process and did not explicitly teach polishing the thinned substrate. Poole was cited for its disclosure of a well-known two-step process for thinning semiconductor substrates that involves both grinding and chemical mechanical polishing (CMP) to achieve a smooth, planar surface with minimal defects, thinned to 10 µm.
    • Motivation to Combine: A POSITA would combine these references by replacing the wet etching process of Bertin ’754 with the superior two-step thinning and polishing process of Poole. The motivation was to achieve a simpler manufacturing process (eliminating Bertin ’754's required etch stop layer) and a more predictable, planar surface finish. A planar surface was known to be critical for forming reliable vertical interconnects and bonds between substrates, a key goal in both references.
    • Expectation of Success: Success was expected because this combination represented a simple substitution of one known thinning method for another to achieve the predictable result of a thin, smooth substrate suitable for stacking.

Ground 2: Claims 10-12, 18-20, 60-63, 67, 70-73, and 77 are obvious over Bertin ’754, Poole, and Leedy ’695.

  • Prior Art Relied Upon: Bertin ’754 (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address claim limitations requiring a "low stress dielectric." While Bertin ’754 disclosed using a dielectric layer (SiO2), it did not specify it was "low stress" or had a particular tensile stress value. Leedy ’695, whose inventor is the same as the ’239 patent, was cited for its explicit disclosure of fabricating flexible integrated circuits using very thin, low-stress dielectric materials, such as silicon dioxide with a tensile stress of less than 5×10⁸ dynes/cm².
    • Motivation to Combine: A POSITA would be motivated to incorporate the low tensile stress dielectrics from Leedy ’695 into the stacked chip structure of Bertin ’754. Both Bertin ’754 and Leedy ’695 were directed at improving high-density 3D integrated circuits. Leedy ’695 expressly taught that low tensile stress was critical for maintaining surface flatness and structural integrity in thin semiconductor layers, which would directly address stress management challenges inherent in stacking thinned wafers as taught by Bertin ’754.
    • Expectation of Success: Success was reasonably expected because Leedy ’695 taught that its low-stress dielectrics were versatile and could be deposited using well-known techniques like PECVD, making them suitable substitutes for the conventional dielectrics in Bertin ’754 to predictably reduce overall stress in the final stacked device.

Ground 3: Claims 46 and 47 are obvious over Bertin ’754, Poole, and Bertin ’333.

  • Prior Art Relied Upon: Bertin ’754 (Patent 5,202,754), Poole (Patent 5,162,251), and Bertin ’333 (Patent 5,502,333).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground added teachings for the "reconfiguration circuitry" limitation of claim 46. The base combination of Bertin ’754 and Poole provided the stacked, thinned, and polished substrates. Bertin ’333, from the same inventor as Bertin ’754, was introduced for its disclosure of incorporating "reconfiguration circuitry" in a 3D stack. Specifically, Bertin ’333 taught using an electrically programmable spare circuit to functionally replace failed memory cells, thereby improving the yield of the entire stack.
    • Motivation to Combine: A POSITA would combine these references to solve a well-known problem. Stacked memory architectures like that in Bertin ’754 suffered from low yield, as a single failed cell could render an entire expensive stack useless. Bertin ’333 provided a known solution to this exact problem by adding programmable sparing capability. A POSITA would have been motivated to add the reconfiguration circuitry of Bertin ’333 to the stacked structure of Bertin ’754 to improve yield, reduce cost, and increase density.
    • Expectation of Success: The combination was a predictable integration of known solutions to address known problems in the field of 3D ICs.
  • Additional Grounds: Petitioner asserted that claims 60-63, 67, 70-73, and 77 were obvious over the four-way combination of Bertin ’754, Poole, Leedy ’695, and Bertin ’333. Petitioner also asserted several alternative grounds (Grounds 5-9) based on broader claim constructions that would not require certain prior art elements, such as Poole for polishing or Leedy ’695 for low-stress dielectrics.

4. Key Claim Construction Positions

  • "a substantially flexible semiconductor substrate" (claims 1, 13, 46): Petitioner argued this term should be construed as "a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on the applicant acting as its own lexicographer in the specification and making explicit, defining statements during the prosecution of related patents to overcome indefiniteness rejections.
  • "dice" are / "die" is "substantially flexible" (claims 60, 70): For these terms, Petitioner proposed a more stringent construction: "a die [dice] having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This added requirement was based on statements made during prosecution of related applications distinguishing flexible circuit layers from merely flexible substrates.

5. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 10-13, 18-20, 46-47, 60-63, 67, 70-73, and 77 of the ’239 patent as unpatentable.