PTAB

IPR2016-00395

Samsung Electronics Co Ltd v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’732 patent discloses three-dimensional (3D) integrated circuits (ICs) formed by stacking multiple thinned semiconductor layers. The technology focuses on fabrication methods that include thinning substrates to be "substantially flexible," bonding layers together, forming vertical interconnections (vias), and using low tensile stress dielectric materials to manage mechanical stress in the stacked structure.

3. Grounds for Unpatentability

Ground 1: Obviousness over Yu and Leedy ’695

  • Claims 1, 10, 11, 13, and 14 are obvious over Yu in view of Leedy ’695.
  • Prior Art Relied Upon: Yu (a 1996 IEEE conference paper titled "Real-Time Microvision System with Three-Dimensional Integration Structure") and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yu disclosed most limitations of the challenged claims, including a stacked 3D IC structure. Yu taught grinding and polishing silicon substrates to a thickness of approximately 30 µm (less than the claimed 50 µm), forming circuits on them, and stacking them with vertical interconnections. Yu also disclosed using silicon dioxide (SiO₂) as a dielectric insulator. However, Petitioner asserted that Yu did not explicitly disclose that its dielectric layers were "low stress." Leedy ’695, whose inventor is also the inventor of the ’732 patent, was argued to supply this missing element. Leedy ’695 expressly taught the fabrication of flexible ICs using very thin layers and low tensile stress dielectrics (e.g., silicon dioxide or silicon nitride) with a stress of less than 8 x 10⁸ dynes/cm², which meets the ’732 patent’s stress limitation as construed by Petitioner.
    • Motivation to Combine: Petitioner contended a person of ordinary skill in the art (POSITA) would combine these references because both sought to achieve high-performance 3D ICs. A POSITA would have recognized that managing mechanical stress is a critical challenge in stacking thin wafers, as taught by Yu. Leedy ’695 provided an explicit solution to this known problem by describing how to deposit low-stress dielectric films to improve structural integrity and surface flatness without compromising performance. A POSITA would have been motivated to apply the known stress-reduction technique from Leedy ’695 to improve the reliability and yield of the 3D structure in Yu.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because Leedy ’695 described its low-stress dielectrics as versatile and compatible with conventional IC processing techniques, such as those used in Yu. The combination involved applying a known technique (low-stress dielectric deposition) to a known system (a stacked IC) to achieve a predictable result (improved structural stability).

Ground 2: Obviousness over Finnila, Yu, and Leedy ’695

  • Claims 1, 10, 11, 13, and 14 are obvious over Finnila in view of Yu and Leedy ’695.
  • Prior Art Relied Upon: Finnila (Patent 5,426,072), Yu (1996 IEEE paper), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Finnila disclosed a 3D IC assembly made from stacking multiple thinned Silicon-on-Insulator (SOI) wafers, teaching thicknesses of approximately 12 µm. However, Finnila’s thinning process (etching or lapping) did not explicitly disclose a subsequent polishing step to create a smooth surface. Yu was introduced to supply this teaching, as it described a two-step thinning process of grinding followed by polishing to achieve a planar, smooth surface suitable for bonding. Similar to Ground 1, Petitioner argued that neither Finnila nor Yu explicitly disclosed the use of low-stress dielectrics. Leedy ’695 was again relied upon to teach the use of dielectrics with a tensile stress below the claimed threshold. The combination of the three references was alleged to teach every limitation of the challenged claims.
    • Motivation to Combine: A POSITA would have been motivated to modify Finnila’s thinning process with Yu’s process because achieving a planar and smooth surface is critical for reliable bonding and interconnection in 3D ICs. Yu’s grinding and polishing method was a well-known, reliable technique for achieving this result. Therefore, it would have been an obvious design choice to substitute or supplement Finnila’s method with Yu’s. The motivation to further combine with Leedy ’695 was the same as in Ground 1: to address the known problem of mechanical stress in the stacked structure described by Finnila, thereby improving its structural integrity and manufacturability.
    • Expectation of Success: The combination involved integrating known, compatible semiconductor manufacturing processes. Applying Yu's well-established polishing technique to Finnila's thinned wafers and incorporating Leedy '695's proven stress-management dielectrics would have been straightforward for a POSITA, leading to the predictable outcome of a more robust and reliable 3D IC.

4. Key Claim Construction Positions

  • "substantially flexible integrated circuit layer" (claims 1, 13, 14): Petitioner argued this term was not merely descriptive of physical pliancy but was a term of degree defined by specific manufacturing parameters. Citing the patent's specification and statements made during the prosecution of related applications to overcome prior art, Petitioner proposed the term must be construed to mean "an integrated circuit layer having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction was central to Petitioner's obviousness arguments, as it directly linked the "flexibility" limitation to the "low stress dielectric" taught by Leedy ’695.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1, 10, 11, 13, and 14 of the ’732 patent as unpatentable.