PTAB

IPR2016-00691

SK Hynix Inc v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’004 patent discloses methods for manufacturing three-dimensional (3D) stacked integrated circuits (ICs). The technology involves thinning semiconductor substrates to less than 50 µm to create "substantially flexible" layers, bonding these layers together, and forming vertical interconnections, with an emphasis on using low tensile stress dielectrics to manage mechanical stress and improve yield.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 20-23 are obvious over Finnila, Yu, and Leedy ’695.

  • Prior Art Relied Upon: Finnila (Patent 5,426,072), Yu (a 1996 IEEE conference publication), and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Finnila disclosed the foundational stacked 3D IC structure, including multiple thinned circuit layers with vertical interconnections. However, Finnila did not explicitly teach thinning to less than 50 µm followed by polishing, nor the use of a specific low-stress dielectric as required by Petitioner’s construction of "substantially flexible." Petitioner asserted Yu supplied the missing thinning and polishing steps, describing a process of grinding and then polishing silicon wafers to a thickness of approximately 30 µm to create a smooth, planar surface suitable for 3D bonding. Leedy ’695, which is incorporated by reference in the ’004 patent, was argued to teach the use of low tensile stress dielectrics (e.g., silicon dioxide with stress < 5x10⁸ dynes/cm²) to ensure structural integrity and surface flatness in flexible ICs.
    • Motivation to Combine: A POSITA would combine these references to improve the known 3D IC structure of Finnila. A POSITA would have recognized that the thinning methods in Finnila (etching, lapping) could be replaced with Yu’s well-known grinding and polishing process to achieve a superior smooth surface for reliable bonding. Furthermore, to address known problems of stress and warpage in stacked structures, a POSITA would have been motivated to incorporate the low-stress dielectrics from Leedy ’695 into Finnila’s design, as Leedy ’695 expressly teaches their benefits for structural integrity.
    • Expectation of Success: Success was expected because the combination involved applying known, conventional semiconductor processing techniques (polishing from Yu, low-stress deposition from Leedy ’695) to a known structure (Finnila) to achieve predictable improvements in surface quality and stress management.

Ground 2: Claims 1 and 20-23 are obvious over Finnila, Yu, Leedy ’695, and Blonder.

  • Prior Art Relied Upon: Finnila (Patent 5,426,072), Yu (a 1996 IEEE conference publication), Leedy ’695 (Patent 5,354,695), and Blonder (Patent 4,937,653).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds directly on Ground 1, relying on the combination of Finnila, Yu, and Leedy ’695 for the same reasons. The addition of Blonder was intended to provide a more explicit teaching for the "redundant vertical interconnections" limitation of claim 1. While Finnila suggested redundant circuitry to improve yield, Blonder was argued to expressly disclose using redundant electrically functional pads for chip-to-chip bonding to increase electrical reliability.
    • Motivation to Combine: Petitioner argued that since Finnila already disclosed the goal of improving yield through redundancy, a POSITA would naturally look to other known techniques for achieving this, such as those in Blonder. Blonder addresses the same technical context of chip-to-chip bonding and provides a clear, known solution for improving reliability. A POSITA would combine Blonder's specific teaching on redundant interconnects with the Finnila/Yu/Leedy ’695 structure to enhance the overall yield and reliability of the final stacked device.
    • Expectation of Success: The expectation of success was high, as providing redundancy is a fundamental design principle in IC manufacturing to improve yield, and Blonder demonstrated a straightforward method to implement it.

Ground 3: Claims 1 and 20-23 are obvious over Yu, Leedy ’695, and Blonder.

  • Prior Art Relied Upon: Yu (a 1996 IEEE conference publication), Leedy ’695 (Patent 5,354,695), and Blonder (Patent 4,937,653).

  • Core Argument for this Ground:

    • Prior Art Mapping: In this ground, Yu served as the primary reference, disclosing a stacked 3D IC structure with multiple layers thinned to 30 µm by grinding and polishing. Petitioner contended that Yu taught the core elements of the claims, including a plurality of thinned circuits in a stacked arrangement. Leedy ’695 was added to provide the teaching of using low tensile stress dielectrics, which Yu did not explicitly disclose. Blonder was again added to supply the express teaching of redundant vertical interconnections to improve electrical reliability.
    • Motivation to Combine: A POSITA starting with Yu’s 3D IC structure would seek to improve its manufacturability and reliability using known industry techniques. To mitigate stress-related defects common in thin, stacked wafers, the POSITA would be motivated to adopt the low-stress dielectric deposition processes from Leedy ’695. To improve the yield and electrical integrity of the vertical connections shown in Yu, the POSITA would incorporate the redundant interconnect strategy taught by Blonder, a common practice for expensive, complex ICs.
    • Expectation of Success: A POSITA would have reasonably expected success in combining these references, as it represented the application of known solutions (low-stress materials from Leedy ’695, redundancy from Blonder) to solve well-understood problems (stress, yield) in the specific context of 3D ICs (disclosed by Yu).

  • Additional Grounds: Petitioner asserted alternative obviousness challenges (Grounds 4 and 5) over combinations of Finnila, Leedy ’695, and Blonder, to be considered if the Board adopted a broader claim construction that did not require polishing.

4. Key Claim Construction Positions

  • "substantially flexible integrated circuit[s]" (claims 1, 22, and 23): Petitioner argued that this term is not indefinite and should be construed based on the specification and the patent owner's statements during prosecution of related patents. The proposed construction is: "integrated circuit[s] having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5x10⁸ dynes/cm² tensile or less." This construction was central to the petition, as it explicitly imports the key features of thinning, polishing, and low stress into a single claim term, which Petitioner then mapped to the teachings of Yu and Leedy ’695.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1 and 20-23 of the ’004 patent as unpatentable.