PTAB

IPR2016-00708

Micron Technology Inc v. Elm 3DS Innovations LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’499 patent discloses methods for fabricating three-dimensional (3D) integrated circuits (ICs), such as stacked memory. The methods involve thinning semiconductor substrates to less than 50 µm, bonding the thinned substrates to form a vertical stack, and creating vertical interconnections through the substrates, with an emphasis on using low tensile stress dielectric materials to manage stress.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 49 are obvious over Hsu, Leedy ’695, and Sakuta.

  • Prior Art Relied Upon: Hsu (Patent 5,627,106), Leedy ’695 (Patent 5,354,695), and Sakuta (Patent 5,208,782).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hsu disclosed most elements of the challenged claims, including a method for creating 3D stacked ICs by grinding and polishing a semiconductor substrate to a thin layer. However, Hsu did not explicitly teach that the dielectric layer used for insulation had the claimed low tensile stress. Leedy ’695 was introduced to supply this missing element, as it explicitly taught the fabrication of flexible ICs using very thin, low tensile stress dielectric materials (e.g., silicon dioxide with stress < 8 x 10⁸ dynes/cm²) to improve structural integrity. For claim 49, which required the memory circuit to be partitioned into independently operable blocks, Petitioner asserted that Sakuta taught this exact feature in its disclosure of "macro-cellulated memory blocks."
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Hsu and Leedy ’695 because both references aimed to improve 3D IC manufacturing. A POSITA would have been motivated to apply the known low-stress dielectric deposition techniques from Leedy ’695 to Hsu’s 3D structure to improve reliability, durability, and surface flatness. Similarly, a POSITA would incorporate Sakuta’s partitioned memory architecture into Hsu’s 3D stacking method to improve manufacturing yields (by isolating defective blocks) and increase performance through higher memory bandwidth.
    • Expectation of Success: Success would have been expected because Leedy ’695’s low-stress dielectric deposition processes, such as PECVD, were well-known, versatile, and compatible with standard IC fabrication techniques like those described in Hsu.

Ground 2: Claims 1 and 49 are obvious over Bertin ’945, Leedy ’695, Poole, and Sakuta.

  • Prior Art Relied Upon: Bertin ’945 (Patent 5,731,945), Leedy ’695 (Patent 5,354,695), Poole (Patent 5,162,251), and Sakuta (Patent 5,208,782).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Bertin ’945 taught a 3D multichip stack of memory and logic layers where substrates were thinned to 20 µm or less. However, Bertin ’945 taught thinning via wet etching and did not explicitly disclose the subsequent polishing required by Petitioner’s proposed claim construction, nor the use of a low-stress dielectric. Leedy ’695 was again relied upon for its teaching of low tensile stress dielectrics. Poole was introduced to teach a superior two-step thinning process involving grinding followed by chemical mechanical polishing (CMP), which results in a planar, low-defect surface. Sakuta was again used to teach the partitioned memory block structure recited in claim 49.
    • Motivation to Combine: A POSITA would have been motivated to modify Bertin ’945 by incorporating the low-stress dielectrics from Leedy ’695 for improved structural integrity. Petitioner argued a POSITA would also replace the wet etching process of Bertin ’945 with the superior grinding and polishing process from Poole. This was a known alternative that would predictably result in a smoother, more planar surface, which is highly desirable for ensuring reliable bonding and interconnection formation in 3D stacked packages. The motivation to add Sakuta was to gain the known benefits of yield and performance improvement.
    • Expectation of Success: The combination was argued to be a predictable substitution of one known element for another to obtain predictable results.

  • Additional Grounds: Petitioner asserted alternative obviousness challenges under different claim constructions. Ground 3 replaced Leedy ’695 with Kowa (Japanese Patent Pub. H3-151637) for its stress-balancing teachings. Ground 4 was similar to Ground 2 but excluded Poole, to be relied upon if the claims were construed not to require a polishing step.

4. Key Claim Construction Positions

Petitioner dedicated significant argument to the construction of two key terms based on lexicography in the specification and prosecution history.

  • “substantially flexible monocrystalline semiconductor layer” (Claim 1): Petitioner argued this term should be construed as "a semiconductor layer that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on explicit definitions provided by the applicant during prosecution to overcome an indefiniteness rejection.
  • “substantially flexible structure” (Claims 1, 49): Petitioner proposed this term be construed as "a structure having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction added the low-stress requirement, which Petitioner argued was also established by the applicant during prosecution to distinguish over prior art.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1 and 49 of Patent 8,907,499 as unpatentable under 35 U.S.C. §103.