PTAB

IPR2016-00770

Micron Technology Inc v. Elm 3DS Innovations LLC

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Integrated Circuit Memory
  • Brief Description: The ’499 patent discloses methods for fabricating three-dimensional (3D) integrated circuits (ICs), particularly stacked memory. The described methods involve thinning semiconductor substrates to less than 50 µm, bonding them to form a vertical stack, and creating vertical interconnections through the thinned substrates, often utilizing low tensile stress dielectric materials to manage mechanical stress.

3. Grounds for Unpatentability

Ground 1: Obviousness over Hsu and Leedy – Claims 12, 13, 24, 36-38, 53, 83, 86, 87, and 132 are obvious over Hsu in view of Leedy ’695.

  • Prior Art Relied Upon: Hsu (Patent 5,627,106) and Leedy ’695 (Patent 5,354,695).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hsu discloses nearly all features of the challenged claims, including a method for creating 3D stacked memory chips by thinning a "subordinate chip" substrate via grinding and polishing and stacking it on a "master chip." Hsu also discloses forming vertical interconnects through the thinned substrate. The primary feature Petitioner asserted Hsu does not explicitly disclose is the use of a silicon-based dielectric layer with a tensile stress below the claimed threshold of 5×10⁸ dynes/cm². Leedy ’695, which is incorporated by reference in the ’499 patent, was argued to cure this deficiency by teaching the fabrication of flexible ICs using very thin, low tensile stress dielectric materials (e.g., silicon dioxide) to improve structural integrity and durability.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Hsu and Leedy ’695 because both references address the common goal of improving high-density 3D integrated circuits. Leedy ’695 explicitly provides a solution—low-stress dielectrics—for the well-known problems of stress, surface flatness, and structural integrity that arise during the fabrication processes described in Hsu. A POSITA would have been motivated to apply the known stress-management techniques from Leedy ’695 to Hsu’s 3D stacking architecture to improve the overall reliability and manufacturing yield of the resulting device.
    • Expectation of Success: Petitioner asserted a POSITA would have a reasonable expectation of success because Leedy ’695 describes its low-stress dielectrics as versatile and able to withstand a wide range of standard IC processing techniques and temperatures. Therefore, incorporating these known materials into Hsu's process would have been a predictable implementation of a known technique to improve a similar device.

Ground 2: Obviousness over Bertin, Poole, and Leedy – Claims 12, 13, 24, 36-38, 53, 83, 86, 87, and 132 are obvious over Bertin in view of Poole and Leedy ’695.

  • Prior Art Relied Upon: Bertin (Patent 5,202,754), Poole (Patent 5,162,251), and Leedy ’695 (Patent 5,354,695).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Bertin discloses a 3D multichip package with a densely stacked array of semiconductor chips, including thinning substrates to 20 µm or less and forming vertical interconnections. However, Bertin achieves thinning via a wet etching process and does not explicitly teach the subsequent polishing required by Petitioner’s proposed claim construction, nor does it specify the use of low-stress dielectrics. Poole was introduced to supply the teaching of polishing, as it discloses a two-step thinning process that combines grinding with chemical-mechanical polishing (CMP) to produce a substrate thinned to 10 µm with a planar, low-defect surface. Leedy ’695 was again relied upon to teach the use of low tensile stress dielectrics.
    • Motivation to Combine: A POSITA would combine Bertin and Poole by replacing Bertin’s wet etching process with Poole’s superior grinding and CMP method. This was argued to be an obvious substitution of one known thinning technique for another to achieve a predictable improvement: a thinner, more planar substrate, which is critical for reliable bonding in the stacked structure of Bertin. A POSITA would then be motivated to incorporate the low-stress dielectrics of Leedy ’695 into the combined Bertin/Poole framework to manage mechanical stress, a fundamental challenge in 3D IC manufacturing that Bertin’s thermally grown oxides did not optimally address.
    • Expectation of Success: Success would be reasonably expected, as the combination involves substituting known, alternative manufacturing processes (Poole’s thinning, Leedy’s dielectrics) into an existing device architecture (Bertin) to achieve well-understood benefits.

  • Additional Grounds: Petitioner asserted additional obviousness grounds under alternative claim constructions, including a challenge over Hsu and Kowa (Japanese Patent Pub. H3-151637) where Kowa’s stress-balancing technique is substituted for Leedy’s low-stress material, and a challenge over Bertin and Leedy ’695 (excluding Poole) if the claims are construed not to require polishing.

4. Key Claim Construction Positions

Petitioner argued that the patentee acted as its own lexicographer, defining the key term "substantially flexible" during prosecution. The proposed constructions were central to the invalidity arguments.

  • "substantially flexible … semiconductor substrate/layer": Petitioner proposed the construction "a semiconductor substrate [layer] that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed." This construction was based on explicit statements in the ’499 patent’s specification and arguments made by the applicant to overcome an indefiniteness rejection during prosecution, thereby tying the term of degree to objective, structural criteria.
  • "substantially flexible circuit/integrated circuit": Petitioner proposed a broader construction for this term: "a circuit... having a semiconductor substrate that has been thinned to a thickness of less than 50 µm and subsequently polished or smoothed, and where the dielectric material used in processing the semiconductor substrate must have a stress of 5×10⁸ dynes/cm² tensile or less." This construction adds the low-stress dielectric requirement, which Petitioner argued was established as a necessary condition for a flexible circuit (as opposed to just a substrate) during prosecution of related applications.

5. Relief Requested

  • Petitioner requests the institution of an inter partes review and the cancellation of claims 12, 13, 24, 36-38, 53, 83, 86, 87, and 132 of Patent 8,907,499 as unpatentable.