PTAB
IPR2016-00903
Volkswagen Group Of America Inc v. Advanced Silicon Technologies LLC
Key Events
Petition
Table of Contents
petition
1. Case Identification
- Case #: IPR2016-00903
- Patent #: 6,546,439
- Filed: April 15, 2016
- Petitioner(s): Volkswagen Group of America, Inc.
- Patent Owner(s): Advanced Silicon Technologies LLC
- Challenged Claims: 1-32
2. Patent Overview
- Title: Memory Controller with Source Indication for Intelligently Scheduling Memory Accesses
- Brief Description: The ’439 describes a memory controller system designed to more efficiently service memory access requests from a plurality of sources (e.g., CPU, graphics controller). The system provides information about each request, such as a source indication or other parameters, to the memory controller to enable intelligent scheduling and reordering of the requests.
3. Grounds for Unpatentability
Ground 1: Obviousness over Pattin and Lewchuk - Claims 1-7, 10-13, 15, 17-23, 26-29, and 31
- Prior Art Relied Upon: Pattin (Patent 5,745,913) and Lewchuk (Patent 6,058,461).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Pattin taught the core limitations of independent claims 1 and 17, including a memory controller system with a "requested memory operation buffer" (Pattin's request queue) that receives requests from multiple sources. Pattin disclosed that this buffer provides a "source indication" (an identifier in a source field) for each request, which its "request prioritizer" uses to schedule memory accesses. Dependent claims reciting grouping requests, prioritizing open pages, and including parameters like initiator identity, priority indicators, or speculative status were argued to be taught by Pattin's round-robin scheduling, row-hit prioritization, and use of various data fields. Lewchuk was cited as further teaching the use of priority levels to reorder memory operations.
- Motivation to Combine: A POSITA would combine Pattin and Lewchuk to improve system performance. Both references operated in the same field of shared memory systems and addressed the common goal of intelligently scheduling memory requests from multiple sources.
- Expectation of Success: Given the similar memory architectures and goals, a POSITA would have been able to fit the teachings of the two patents together predictably.
Ground 2: Obviousness over Pattin, Lewchuk, and Bauman - Claims 14 and 30
- Prior Art Relied Upon: Pattin (Patent 5,745,913), Lewchuk (Patent 6,058,461), and Bauman (Patent 5,832,304).
- Core Argument for this Ground:
- Prior Art Mapping: This ground built upon the combination of Pattin and Lewchuk to address claims 14 and 30, which required the memory buffer to comprise a separate memory request queue for each source. While Pattin used a single queue with source identifiers, Petitioner argued that Bauman explicitly taught this limitation. Bauman disclosed a memory controller that separates memory requests from different sources (e.g., instruction processors vs. input/output adapters) into respective FIFO queues to prevent one source from dominating memory access and to allow for prioritization between the queues.
- Motivation to Combine: A POSITA would have found it an obvious design choice to incorporate Bauman's separate-queue approach into the Pattin/Lewchuk system. Indicating the source of a request by assigning it to a designated queue (as in Bauman) versus assigning an identification field (as in Pattin) were known, interchangeable techniques for achieving the same goal of source-based prioritization.
- Expectation of Success: Combining these known queuing strategies to improve memory scheduling would yield no unexpected results.
Ground 3: Obviousness over Pattin, Lewchuk, and Wulf - Claims 8, 16, 24, and 32
- Prior Art Relied Upon: Pattin (Patent 5,745,913), Lewchuk (Patent 6,058,461), and Wulf (Patent 6,154,826).
- Core Argument for this Ground:
- Prior Art Mapping: This ground targeted claims requiring the source indication or an associated parameter to comprise an "identity of a stream or thread." Petitioner asserted that Wulf taught this feature. Wulf described a memory scheduling unit that reordered memory accesses from a plurality of "streams," with each stream assigned to a specific FIFO queue. Wulf disclosed that the "head" of each FIFO stores a value identifying the stream assigned to it, which constituted the claimed "identity of a stream or thread."
- Motivation to Combine: A POSITA would combine Wulf's stream-based processing with the Pattin/Lewchuk memory controller to improve performance for applications like vector processing. Wulf itself noted the practicality of adding its features to existing architectures. It would have been a simple design choice to add a field to Pattin's request queue to store a stream or thread identifier as taught by Wulf.
- Expectation of Success: The combination was presented as a predictable integration of known memory management techniques to enhance performance.
Ground 4: Obviousness over Pattin, Lewchuk, and DiNicola - Claims 9 and 25
- Prior Art Relied Upon: Pattin (Patent 5,745,913), Lewchuk (Patent 6,058,461), and DiNicola (Patent 5,394,524).
- Core Argument for this Ground:
- Prior Art Mapping: This ground addressed claims requiring a parameter that indicates whether a memory request can be completed out of order. Petitioner contended that while Pattin recognized that some requests must be processed in order, it did not explicitly describe how to indicate this. DiNicola, in the context of reordering graphics data, taught assigning synchronization tags or sequence numbers to work groups to indicate whether they were "order-dependent" or "order-independent," which a reordering device then used to schedule processing.
- Motivation to Combine: A POSITA would be motivated to apply DiNicola's explicit order-dependency indication scheme to the more general-purpose memory controller of Pattin/Lewchuk to improve scheduling flexibility. Adding a field to Pattin's request queue to hold a sequence number or order-dependency flag from DiNicola was argued to be a natural and predictable improvement.
- Expectation of Success: Implementing DiNicola's synchronization tag scheme within Pattin's system was a straightforward design choice to solve a known problem in memory reordering.
4. Key Claim Construction Positions
- "source indication": Petitioner proposed construing this term as "information that can be used to determine the source of the request." This construction was argued to be consistent with the specification's disclosure that queues associated with specific buses "convey information about the sources."
- "tag": Petitioner proposed construing this term as "a data structure that includes information associated with a memory access request." This was based on the specification describing a tag as containing "one or more units indicative of one or more parameters related to the transaction in question."
5. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 1-32 of the ’439 as unpatentable.
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