PTAB

IPR2016-00940

Sony Corp v. Collabo Innovations Inc

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Key Events
Petition
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1. Case Identification

2. Patent Overview

  • Title: Solid-State Image Sensor
  • Brief Description: The ’724 patent discloses a solid-state imaging device and methods for its construction intended to reduce defects, such as dark current, that occur when forming through-holes for electrodes. The purported invention involves structuring semiconductor layers so that a through-hole penetrates a region of only a single conductivity type, avoiding the creation of defects at a PN junction.

3. Grounds for Unpatentability

Ground 1: Anticipation over Admitted Prior Art - Claim 1 is anticipated by the Admitted Prior Art (APA).

  • Prior Art Relied Upon: Admitted Prior Art (APA) disclosed in the ’724 patent specification, particularly the description of conventional devices in the "Background of the Invention" section and associated Figs. 12, 13A, and 13B.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the ’724 patent’s own description of a conventional solid-state imaging device discloses every element of independent claim 1. The APA teaches a device with a semiconductor substrate, an imaging region, a peripheral circuit region, multiple semiconductor layers of first and second conductivity types, a through electrode, a pad portion, and a side insulating film. Petitioner contended that claim 1 is critically broad because it does not recite the purported inventive feature of avoiding etching across a PN junction. Since the conventional device described in the APA explicitly includes a through-hole that does cross a PN junction, it falls within the scope of and therefore anticipates claim 1.

Ground 2: Obviousness over APA and Shibayama - Claims 2-4 are obvious over the APA in view of Shibayama.

  • Prior Art Relied Upon: Admitted Prior Art (APA) and Shibayama (Japanese Pat. App. Pub. No. P2004-165602A).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that the additional limitations of dependent claims 2-4 are disclosed by Shibayama.
      • For claim 2, which requires the through-hole to penetrate only a first conductivity type area, Petitioner argued Shibayama expressly teaches this feature. Shibayama discloses creating through-holes that penetrate only an N-type substrate to reduce mechanical damage and resulting dark current.
      • For claim 3, which adds a third semiconductor layer around the through electrode, Petitioner pointed to Shibayama’s disclosure of forming high impurity concentration N-type layers along the wall faces of through-holes to trap unnecessary carriers.
      • For claim 4, which requires this third layer to extend from the main surface to an opposite surface, Petitioner argued Shibayama teaches this by showing the carrier-trapping layers extending from the front to the rear of the substrate.
    • Motivation to Combine: Petitioner argued that both the APA and Shibayama identify the same problem of dark current caused by mechanical damage from forming through-holes. A person of ordinary skill in the art (POSITA) would have been motivated to apply Shibayama’s known technique—forming through-holes within a single conductivity region and adding trapping layers—to the conventional device of the APA to solve this well-understood problem and achieve the predictable result of reduced dark current.
    • Expectation of Success: The proposed modification was argued to be a straightforward combination of known elements to solve a known problem, yielding predictable results well within the ordinary skill of a POSITA to implement.

Ground 3: Obviousness over Asano - Claims 1 and 2 are obvious over Asano.

  • Prior Art Relied Upon: Asano (WO 2006/073085 A1).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner contended that Asano, which discloses a solid-state image pickup device, teaches all elements of claims 1 and 2. Asano shows a substrate with photoreceiving sections (imaging region), a peripheral section with electrodes and protection diodes (peripheral circuit), penetrating electrodes, and a side insulating film. Petitioner argued that while Asano does not explicitly state its photodiodes are arranged "two-dimensionally," this would be an obvious and necessary feature for any device described as an "image pickup device." Crucially, Petitioner asserted that an embodiment in Asano expressly shows through-holes penetrating only through the N-type substrate, thus meeting the limitation of claim 2.
    • Motivation to Combine (for obvious elements): The motivation to include features like a two-dimensional photodiode array was argued to be inherent in the goal of creating a functional image sensor, as disclosed by Asano for use in cameras.
    • Expectation of Success: A POSITA would have easily and successfully implemented a 2D array in Asano’s device to achieve its stated purpose.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claims 3 and 4 over Asano in view of Shibayama, claims 1 and 2 over Yanagida (Japanese Pat. App. Pub. No. P2006-23497A), and claims 3 and 4 over Yanagida in view of Holm (Application # 2006/0043438). These grounds relied on similar arguments that known techniques for reducing dark current would have been obvious to apply to conventional image sensor designs.

4. Key Claim Construction Positions

  • "Peripheral Circuit Region … Formed in an Outer Peripheral Portion of the Imaging Region" (Claim 1): Petitioner argued this phrase should be construed to mean a region formed near the outer portions of the imaging region, regardless of whether it is inside or outside that region. This construction was based on the ordinary meaning of "peripheral" and asserted inconsistencies in the patent’s specification.
  • "at a side of the main surface" (Claim 1): Petitioner proposed this should mean "on the same side of the substrate as the main surface" (i.e., the front or top surface where the imaging region is located), based on the specification's consistent use of "front side" and "rear side."
  • "Semiconductor Layer" (Claims 1 & 3): Petitioner argued for a broad construction of "a semiconductor region having particular electrical properties" (e.g., N-type or P-type conductivity), consistent with its usage in the patent and the art.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4 of the ’724 patent as unpatentable.