Texas Instruments Inc v. Advanced Silicon Technologies LLC

1. Case Identification

• Case #: IPR2016-01108
• Patent #: 8,933,945
• Filed: May 27, 2016
• Petitioner(s): Texas Instruments Incorporated
• Patent Owner(s): Advanced Silicon Technologies, LLC
• Challenged Claims: 1-11 and 21

2. Patent Overview

• Title: Graphics Processing Circuitry Utilizing Tile-Based Screen Partitioning
• Brief Description: The ’945 patent relates to graphics processing circuitry that divides rendering operations among multiple graphics pipelines. The purported invention is a system that partitions a display into a repeating pattern of tiles and assigns specific pipelines to process data for dedicated sets of tiles to improve load balancing compared to prior art strip-based partitioning.

3. Grounds for Unpatentability

Ground I: Claims 1, 9, 10, and 21 are obvious over Balmer in view of Narayanaswami.

• Prior Art Relied Upon: Balmer (Patent 5,226,125) and Narayanaswami (Patent 5,757,385).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Balmer discloses the necessary single-chip multiprocessor hardware platform, including multiple parallel processors, a shared memory, and a memory controller (transfer processor and crossbar switch). Narayanaswami was argued to disclose the claimed graphics processing method, including partitioning a display into a repeating tile pattern and assigning processors to process data for dedicated tiles in a round-robin fashion ("processor ownership"). The combination of Balmer’s hardware and Narayanaswami’s algorithm allegedly meets all limitations of independent claims 1 and 21. For example, Balmer’s parallel processors on a single chip function as the claimed "graphics pipelines," and its transfer processor acts as the "memory controller on the chip" that communicates with the pipelines and shared memory. Narayanaswami supplies the "repeating tile pattern" and the logic for assigning each pipeline to a "dedicated tile."
  • Motivation to Combine: A POSITA would combine these references because they are both directed to graphics processing. It would have been obvious to implement Narayanaswami’s known tile-based processing algorithm on Balmer’s versatile and well-suited single-chip hardware platform to achieve known benefits of system-on-chip integration, such as reduced footprint, lower power consumption, increased performance from wider busses, and reduced cost.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because implementing a known graphics algorithm (Narayanaswami) on a general-purpose parallel processing architecture designed for graphics (Balmer) was a conventional and predictable design approach.

Ground II: Claims 2 and 3 are obvious over Balmer and Narayanaswami in view of Furtner.

• Prior Art Relied Upon: Balmer (Patent 5,226,125), Narayanaswami (Patent 5,757,385), and Furtner (Patent 6,778,177).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground I and adds Furtner to address the dependent limitations of claims 2 and 3. Furtner was asserted to explicitly disclose partitioning memory in a two-dimensional tiled manner (claim 2) and that this partitioned memory can be a frame buffer (claim 3).
  • Motivation to Combine: A POSITA would be motivated to incorporate Furtner’s memory tiling technique into the Balmer/Narayanaswami system to enhance memory performance, particularly for rasterizing graphic primitives that extend across multiple tiles, which was a known problem. Furtner explicitly teaches its method provides increased performance.
  • Expectation of Success: The combination was argued to be predictable, as applying a known memory organization technique (Furtner) to a graphics processing system to improve performance is a standard engineering practice.

Ground III: Claims 4-8 and 11 are obvious over Balmer and Narayanaswami in view of Foley.

• Prior Art Relied Upon: Balmer (Patent 5,226,125), Narayanaswami (Patent 5,757,385), and Foley (a 1997 computer graphics treatise).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground addresses dependent claims requiring specific "front end circuitry" and "back end circuitry." Petitioner argued that Narayanaswami’s disclosed processing steps (e.g., lighting calculations, scan conversion, pixel processing) correspond to the functions of these circuitries. Foley, a well-known treatise, was used to establish that these functional blocks were conventional components of graphics pipelines and could be implemented in either hardware or software as an obvious design choice.
  • Motivation to Combine: A POSITA implementing the Narayanaswami algorithm on the Balmer hardware would naturally and obviously structure the implementation using the conventional front-end/back-end pipeline model described in Foley. It would have been a routine design choice to map the functional processing steps of Narayanaswami onto Balmer's parallel processors to create the claimed circuitry.
• Additional Grounds: Petitioner asserted an additional ground (Ground IV) arguing claims 8 and 11 are obvious over Balmer, Narayanaswami, and Foley in view of Kelleher (Patent 5,794,016). Kelleher was used as an alternative to show a known method of programming pipelines with tile identification data using internal configuration registers, which would reduce memory access and increase speed.

4. Key Claim Construction Positions

• "repeating tile pattern": Petitioner argued for a construction of "at least two tiles in a column, and two tiles in a row," asserting that the patent does not require the pattern to repeat in any particular manner beyond this minimum configuration.
• "N×M number of pixels": Based on arguments made during prosecution to distinguish prior art, Petitioner contended this term should be construed as "a rectangular block of pixels that is not square." This construction was argued to be critical for the patentability of claim 21 over prior art that disclosed only square tiles.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §325(d) would be inappropriate because none of the asserted grounds were considered by the Examiner during prosecution. Specifically, the primary combination of Balmer and Narayanaswami was new art. The petition also argued it presented different grounds than those in other co-pending IPRs filed against the ’945 patent.

6. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-11 and 21 of the ’945 patent as unpatentable.