PTAB

IPR2016-01402

Intel Corp v. Future Link Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method for Effecting the Controlled Shutdown of Data Processing Units
  • Brief Description: The ’439 patent describes a method for reducing power consumption in a digital signal processor (DSP) by selectively shutting down data processing units. The method uses two distinct signals: an external hardware-related signal to switch off the clock supply to all unused units, and an internal software-related signal to switch off the clock supply to particular, targeted unused units.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 4 are obvious over Nikjou in view of Rupp.

  • Prior Art Relied Upon: Nikjou (Patent 5,918,061) and Rupp (Patent 5,784,636).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Nikjou discloses the core inventive concept of the ’439 patent: a two-signal approach for power management. Specifically, Nikjou teaches using an external hardware reset signal to shut down all processing units and an internal, software-based HALT instruction to shut down particular processing units. Petitioner noted that during the original prosecution, the patent examiner repeatedly rejected the claims over Nikjou on this basis. The applicant only secured allowance by amending the claims to specify that the method is performed in a "Single Instruction Multiple Data (SIMD)" signal processor. Rupp was introduced to cure this deficiency, as it explicitly discloses a reconfigurable SIMD signal processor that utilizes parallel processing and includes methods for clock gating to save power. The combination of Nikjou’s two-signal control method with Rupp’s SIMD architecture was alleged to render all limitations of claim 1 obvious. For dependent claim 4, Petitioner asserted that Nikjou’s HALT instruction and its disclosure of keeping memory interfaces operational while a DSP is stopped met the additional limitations.
    • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to combine the references. Both Nikjou and Rupp are directed at the same goal: improving power conservation in processors by deactivating unused functional units. A POSITA would have sought to implement Nikjou's established dual-signal power management technique within a high-performance, well-known processor architecture like the SIMD processor taught by Rupp. This combination would predictably achieve both improved power efficiency and the high-performance parallel processing capabilities inherent to SIMD architectures.
    • Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying a known power-saving methodology (Nikjou) to a standard, compatible processor architecture (Rupp) to achieve the predictable result of a power-efficient, high-performance processor.

Ground 2: Claims 1 and 4 are obvious over Nikjou in view of Rodgers.

  • Prior Art Relied Upon: Nikjou (Patent 5,918,061) and Rodgers (Patent 6,357,016).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented a similar argument to Ground 1, again relying on Nikjou for the foundational two-signal power-saving method. To meet the SIMD limitation, Petitioner relied on Rodgers, which discloses a multithreaded processor capable of executing SIMD instructions. Rodgers teaches disabling clock signals to reduce power consumption and discloses both an external hardware RESET signal that stops clocks to all processing units and internal software-generated events (e.g., a HALT instruction) that can suspend clock signals to particular functional units on a unit-by-unit basis. Petitioner argued this combination taught every element of claim 1. For claim 4, Petitioner mapped Rodgers’s teaching of executing a HALT instruction to halt specific threads, while other processor components like the memory execution unit remain active, to the claim’s limitations.
    • Motivation to Combine: Petitioner asserted multiple motivations. Both references address the common problem of reducing power consumption by gating clock signals to inactive units. A POSITA would have been motivated to combine Nikjou's power management system with the SIMD-capable processor in Rodgers to gain both power savings and the known performance benefits of SIMD instructions. Furthermore, Petitioner argued that since Nikjou references Intel’s x86 architecture, a POSITA would have been naturally led to consider other Intel patents related to that architecture, such as Rodgers, to find solutions for implementing high-performance features like SIMD processing.
    • Expectation of Success: The combination was presented as a predictable integration of known technologies. Implementing Nikjou's power management in the SIMD-capable processor of Rodgers was a straightforward design choice that would predictably result in a processor with enhanced performance and lower power consumption.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1 and 4 of the ’439 patent as unpatentable.