PTAB

IPR2016-01553

Samsung Electronics Co Ltd v. TiVo Inc

Key Events

Petition

petition Intelligence

Case #: IPR2016-01553
Patent #: 7,558,472
Filed: August 12, 2016
Petitioner(s): Samsung Electronics Co., Ltd. and Samsung Electronics America, Inc.
Patent Owner(s): TiVo Inc.
Challenged Claims: 1, 12-16, 20, 22, 23, 30, and 32

Title: Multimedia Signal Processing System
Brief Description: The ’472 patent describes a system for the real-time capture, storage, and display of television broadcast signals. The system architecture includes an input section to acquire a signal, and an output section comprising a processor (CPU), a decoder/graphics subsystem, and a media switch with a media manager that operates asynchronously from the CPU to manage data flow between components like a storage subsystem.

Prior Art Relied Upon: MacInnis (Patent 6,853,385).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that MacInnis discloses every element of the challenged claims. MacInnis describes an integrated circuit for processing and displaying video that maps directly to the claimed system. For independent claim 1, MacInnis’s inputs for receiving transport streams (Fig. 38) constituted the claimed “input section.” Its integrated circuit, including a CPU, memory, and I/O bus, formed the “output section.” Petitioner mapped MacInnis’s graphics accelerator and system bridge controller to the claimed “media switch” and “media manager,” and its memory controller and I/O bus bridge to the required host controller, DMA controller, and bus arbiter. The key limitation of simultaneous storage and retrieval was allegedly met by MacInnis’s disclosure of a transport recorder and a playback circuit (PVR) with two independent channels, allowing one to store data while the other plays it back.
- Key Aspects: The core of the anticipation argument relied on mapping various functional blocks within MacInnis's complex integrated circuit design to the specific components recited in the claims of the ’472 patent.

Prior Art Relied Upon: MacInnis (Patent 6,853,385).
Core Argument for this Ground:
- Prior Art Mapping: This ground asserted that even if MacInnis does not explicitly disclose the simultaneous storage and retrieval of multimedia data, it renders the feature obvious. MacInnis discloses a unified memory architecture where multiple clients (e.g., CPU, graphics accelerator) access the memory controller.
- Motivation to Combine (for §103 grounds): Petitioner argued that MacInnis separately teaches a dual memory controller system (Fig. 32) where two controllers can be "accessed concurrently by different clients." A person of ordinary skill in the art (POSITA) would have been motivated to apply this dual-controller teaching to MacInnis’s primary embodiment to improve performance and allow for the concurrent memory access required for simultaneous storage and retrieval.
- Expectation of Success: A POSITA would have had a high expectation of success as this modification involved applying a known technique (dual-memory controllers) to improve a known system architecture for a predictable result.

Prior Art Relied Upon: MacInnis (Patent 6,853,385) and Meandzija (WO 00/24192).
Core Argument for this Ground:
- Prior Art Mapping: This ground addressed claims 22 and 23, which require the processor to run system software, middleware, and application software. Petitioner asserted that MacInnis discloses a hardware system with a CPU capable of implementing software functions. Meandzija discloses a layered software architecture framework for a set-top box, explicitly detailing a hardware layer, an operating system layer (system software), and a middleware/applications layer.
- Motivation to Combine: A POSITA would combine these references to implement Meandzija’s flexible and modular software framework on MacInnis’s capable hardware. This would allow for easier integration with different operating systems and CPUs and simplify application development via Meandzija’s proposed Application Program Interface (API), a well-understood engineering goal.
- Expectation of Success: The combination was argued to be a straightforward implementation of a known software architecture on a suitable hardware platform, presenting no significant technical hurdles.

media switch: Petitioner adopted the Patent Owner’s proposed construction of "hardware and/or code that mediates between a microprocessor CPU, hard-disk or storage device, and memory." This construction was central to mapping components of MacInnis, such as its graphics accelerator, to the claimed switch.
media manager: Petitioner proposed that this term means "the portion of the output section that interfaces with a plurality of system components." This interpretation supported the argument that MacInnis’s memory controller and I/O bus bridge, which interface with multiple peripherals, constituted the claimed media manager.

Priority Date Challenge: A foundational argument of the petition was that the challenged claims were not entitled to the earlier filing dates of the parent '389 patent or the '856 provisional application. Petitioner contended that key limitations of claim 1—including the "media manager," "host controller," "bus arbiter," and the specific architecture where the output section includes the media switch—lacked written description support in the earlier applications. Because this was new matter added in the continuation-in-part ’472 patent application, Petitioner argued the claims' effective priority date is the filing date of the ’472 patent itself (August 22, 2001). This later priority date was critical for establishing that MacInnis and Meandzija qualify as prior art under §102.

Petitioner requested institution of an inter partes review and cancellation of claims 1, 12-16, 20, 22, 23, 30, and 32 of the ’472 patent as unpatentable.