PTAB

IPR2016-01561

Apple Inc v. Limestone Memory Systems LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Memory Device
  • Brief Description: The ’181 patent relates to semiconductor memory devices, particularly dynamic random access memories (DRAM). The technology addresses the inefficient use of spare memory cells by disclosing a device where an array of spare memory cells can be shared among a plurality of memory blocks to replace defective cells.

3. Grounds for Unpatentability

Ground 1: Claim 3 is obvious over Sukegawa in view of Fujishima

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040) and Fujishima (Patent 5,267,214).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sukegawa alone renders obvious the limitations of claims 1 and 2, from which claim 3 depends. Sukegawa disclosed a DRAM device with multiple memory blocks aligned in a column direction and an "ANY TO ANY" redundancy scheme where spare word lines in one block could replace defective word lines in any other block. Petitioner asserted this mapped to the core limitations of claims 1 and 2 concerning a plurality of memory blocks and a shared spare cell capability. The additional limitation in claim 3—"a plurality of sense amplifier bands provided between... and shared by adjacent memory blocks"—was not expressly taught by Sukegawa but was disclosed by Fujishima. Fujishima described a DRAM architecture with a shared sense amplifier arrangement as a well-known, conventional countermeasure to accurately sense data in ever-smaller memory cells. The arrangement shown in Fujishima, described as an "alternate arrangement type shared sense amplifier scheme," was argued to be virtually identical to that claimed.
    • Motivation to Combine: Petitioner contended that a person of ordinary skill in the art (POSITA) would combine Sukegawa and Fujishima because both address DRAM design and architecture. Fujishima explicitly taught that its shared sense amplifier arrangement provided predictable benefits, including improved sensing accuracy, reduced parasitic capacitance, and lower power consumption. These were well-known design goals in the field of DRAM development. A POSITA seeking to improve the performance of the DRAM disclosed in Sukegawa would have naturally looked to known techniques like the shared sense amplifier architecture detailed in Fujishima to achieve these benefits.
    • Expectation of Success: The petition asserted a high expectation of success, as shared amplifier bands were a well-known design choice for DRAMs by 1997. The ’181 patent itself admitted that sharing sense amplifiers between adjacent memory blocks was known in the prior art. The combination involved applying a known technique (Fujishima's shared sense amplifiers) to a known device (Sukegawa's DRAM) to yield predictable results.

Ground 2: Claim 5 is obvious over Sukegawa in view of Fujishima and Walck

  • Prior Art Relied Upon: Sukegawa (Patent 5,487,040), Fujishima (Patent 5,267,214), and Walck (Patent 4,967,397).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination for claim 3. Claim 5 adds limitations requiring the memory blocks and sense amplifier bands to form a "first memory array," the device to comprise a "second memory array having a same arrangement," and "control circuitry" for driving the arrays in two modes. The first mode is a "normal operation mode" where one memory block is selected, and the second is a "particular operation mode" where a prescribed number of blocks are driven simultaneously. Petitioner argued Sukegawa disclosed a device with eight identical memory arrays (called "quadrants"), satisfying the first and second memory array limitations. The control circuitry limitation was met by Walck. Walck disclosed a "Dynamic RAM controller" for large DRAMs with multiple banks (arrays). Walck’s control circuitry enabled a normal mode where one bank is selected for READ/WRITE access and a special refresh mode where all banks are simultaneously activated to refresh data.
    • Motivation to Combine: Petitioner argued that a POSITA building the multi-array DRAM taught by the Sukegawa/Fujishima combination would necessarily require control circuitry. Walck was directly analogous art, teaching control logic for the exact type of large-scale, multi-bank DRAM described. Since memory refresh is a fundamental requirement for DRAM, a POSITA would have been motivated to include the well-known refresh capability disclosed by Walck. Walck taught that its circuitry was useful for large-scale DRAMs and that simultaneous refresh was a traditional method.
    • Expectation of Success: The integration of control circuitry, including for a standard refresh cycle, was a routine and necessary task in DRAM design. Applying Walck's conventional control scheme to the DRAM architecture of Sukegawa/Fujishima would have been a straightforward implementation with a high expectation of success, as it involved combining known elements for their intended purposes.

4. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 3 and 5 of the ’181 patent as unpatentable.