Apple Inc v. Limestone Memory Systems LLC

1. Case Identification

• Case #: IPR2016-01567
• Patent #: 5,894,441
• Filed: August 12, 2016
• Petitioner(s): Apple Inc.
• Patent Owner(s): Limestone Memory Systems LLC
• Challenged Claims: 6-12, 14, and 15

2. Patent Overview

• Title: Semiconductor Memory Device with Redundancy Circuitry
• Brief Description: The ’441 patent relates to redundancy circuits in semiconductor memory devices like DRAM. The disclosed invention aims to improve the efficiency of replacing defective memory cells by using a column redundancy decoder that receives both column address and row address information, enabling the replacement of only a defective portion of a memory column rather than the entire column.

3. Grounds for Unpatentability

Ground 1: Claims 6-12, 14, and 15 are anticipated under 35 U.S.C. §102(b) by Horiguchi.

• Prior Art Relied Upon: Horiguchi (Patent 5,265,055).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Horiguchi discloses every element of the challenged claims. Horiguchi describes a DRAM with a divided bit-line architecture featuring memory sub-arrays with both normal and spare bit lines. Petitioner contended that Horiguchi’s redundancy control circuit (500) meets the limitations of the claimed "column redundancy decoder." This circuit receives both column and row address signals and compares them against stored addresses of defective cells. Upon detecting a match, it activates redundant column selection lines to replace defective memory cells on a bit-by-bit basis. This architecture, which uses row address information to control column redundancy, was asserted to directly read on the key limitations of independent claim 6 and its dependent claims.

Ground 2: Claims 6, 7, 9, 11, 12, 14, and 15 are anticipated under 35 U.S.C. §102(b) by Gallia.

• Prior Art Relied Upon: Gallia (Patent 5,126,973).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Gallia independently anticipates the challenged claims. Gallia teaches a memory device partitioned into arrays, where redundancy is achieved by replacing defective column sections. Petitioner mapped Gallia’s "fusible comparator decoder" (40) to the ’441 patent’s "column redundancy decoder." This decoder in Gallia explicitly receives both column address signals and row address signals to define a level of segmentation for repairs. This use of both row and column address information allows a single redundant column to be segmented to replace defective portions in different columns, thereby satisfying the core inventive concept of the ’441 patent.

Ground 3: Claims 8 and 10 are obvious over Gallia in view of Horiguchi.

• Prior Art Relied Upon: Gallia (Patent 5,126,973) and Horiguchi (Patent 5,265,055).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of Gallia and Horiguchi renders dependent claims 8 and 10 obvious. These claims require that the normal column decoder be inhibited when the redundancy circuit is activated. Gallia provides the primary memory architecture with a column redundancy decoder responsive to row addresses but achieves redundancy by disconnecting data lines rather than explicitly inhibiting the normal decoder. Horiguchi, however, explicitly discloses inhibiting its normal Y-decoder via a NOR gate (504) whenever its redundancy control circuit detects a defective cell.
  • Motivation to Combine: A POSITA would combine these references as they address the same well-known problem of improving redundancy efficiency in DRAMs from the same time period. Inhibiting the normal decoder when a redundant element is selected is a fundamental design principle to prevent signal interference and data errors. Petitioner argued that a POSITA, seeking to implement Gallia’s segmented redundancy scheme, would have found it obvious to incorporate the known, simpler, and complementary decoder inhibition technique taught by Horiguchi to ensure proper operation.
  • Expectation of Success: A POSITA would have had a high expectation of success, as combining the two teachings involved applying a standard and well-understood logic gate function (Horiguchi's NOR gate) to a conventional memory architecture (Gallia) to achieve a predictable and necessary result.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the grounds presented are not redundant to those in a previously filed IPR against the same patent (IPR2016-00094, filed by Micron). That petition, which relied on different prior art (McAdams and Minami), was denied institution because it allegedly failed to show a column redundancy decoder activated in response to a first column address when a second word line is activated. Petitioner asserted that Horiguchi and Gallia explicitly disclose this feature, making the current grounds substantively different and stronger, thus warranting institution.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 6-12, 14, and 15 of the ’441 patent as unpatentable.