PTAB

IPR2016-01589

Semiconductor Components Industries LLC doing Business As On Semiconductor v. Power Integrations Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Generating a Switching Frequency in a Power Conversion System
  • Brief Description: The ’876 patent discloses methods for reducing electromagnetic interference (EMI) in switch mode power supplies (SMPSs) by introducing "jitter" to the switching frequency. The invention describes both digital and analog embodiments for cyclically varying the oscillator frequency by combining a primary current/voltage with a time-varying secondary current/voltage.

3. Grounds for Unpatentability

Ground 1: Anticipation over Dobkin - Claims 11 and 13 are anticipated by Dobkin under 35 U.S.C. §102.

  • Prior Art Relied Upon: Dobkin (Patent 5,929,620).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Dobkin discloses every element of claims 11 and 13. Dobkin teaches an SMPS that reduces noise by varying its voltage-controlled oscillator (VCO) frequency in a controlled manner. This is achieved using a signal generator that produces a time-varying signal (e.g., a sawtooth wave) applied to a secondary current source (126). This secondary current combines with a primary current (from source 128) at the oscillator's control input to vary the switching frequency over time. Petitioner asserted this directly maps to the claimed method of generating a primary current, cycling a secondary current source to create a variable secondary current, and combining them at an oscillator input.
    • Key Aspects: This ground asserted that Dobkin’s analog jitter injection topology, which uses a signal generator to modulate a current source, is the same basic jitter concept as the analog embodiment of the ’876 patent.

Ground 2: Obviousness over Martin and Manlove - Claims 11-13 are obvious over Martin in view of Manlove under 35 U.S.C. §103.

  • Prior Art Relied Upon: Martin (Patent 4,638,417) and Manlove (Patent 5,699,024).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Martin discloses the high-level digital jitter architecture claimed: a power supply that uses a looped configuration where an oscillator output clocks a counter, which addresses an EPROM to drive a Digital-to-Analog Converter (DAC), which in turn controls the oscillator frequency. However, Martin did not disclose low-level implementation details for the DAC or the oscillator. Manlove allegedly supplied these missing details, disclosing a specific relaxation oscillator and a binary-weighted current DAC suitable for SMPSs. Manlove teaches combining a primary current source with a plurality of secondary current sources (the DAC) to control an oscillator's frequency based on a digital input.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) seeking to implement Martin’s high-level block diagram would have looked to well-known circuit designs for the functional blocks. A POSITA would combine Martin's system with Manlove’s specific DAC and relaxation oscillator circuits, as they were known general-purpose components for varying oscillator frequency in SMPSs. This combination was argued to be an obvious implementation of Martin's design to yield predictable results.
    • Expectation of Success: The combination involved implementing Martin's functional blocks with Manlove's known transistor-level circuits, which would predictably result in an SMPS with digital frequency jitter.

Ground 3: Anticipation over Habetler - Claims 17 and 18 are anticipated by Habetler under 35 U.S.C. §102.

  • Prior Art Relied Upon: Habetler (a 1991 IEEE article).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground targeted the voltage-based method claims 17 and 18. Petitioner argued Habetler discloses a random carrier pulse width modulator (PWM) regulator that combines two voltages to modulate the switching frequency. Habetler shows an "average slope" signal (the primary voltage) being combined with a jitter signal from a DAC at a voltage summer. The DAC output is controlled by a ROM, which stores periodic random numbers, thereby "cycling" the secondary voltage source. The combined voltage is fed to the control input of a voltage-controlled oscillator (triangle generator and peak detector). Petitioner asserted that Habetler's counter is clocked by the output of this oscillator, meeting the limitation of dependent claim 18.

  • Additional Grounds: Petitioner asserted numerous other obviousness challenges. These included combining Dobkin with Martin to add a counter-based digital signal generator; combining Dobkin with Stone (a 1996 IEEE article) to arrive at specific claimed current ratios for reducing output ripple; and combining Dobkin/Stone with Manlove to implement the jitter generation with a binary-weighted DAC. Further grounds challenged claims 17-19 using Habetler in view of Martin and/or Marchio (an EP Application) to teach a counter directly coupled to a DAC without an EPROM. Finally, claim 32 was challenged as obvious over Dobkin, Danstrom (Patent 5,638,031), and Grebene (an analog design textbook) for disclosing the claimed analog two-oscillator architecture in a transformer-based SMPS.

4. Key Claim Construction Positions

  • "cycling one or more secondary current [or voltage] sources to generate a secondary current [or voltage] which varies over time" (claims 11 and 17): Petitioner argued for a broad construction of "causing at least one source to generate a time varying signal that repeats." Petitioner contended that the Patent Owner's previous, narrower interpretation—which implicitly required a counter directly coupled to a DAC and a non-randomized variation—was erroneous. Petitioner argued its broader construction was necessary to avoid excluding the patent's own analog embodiment, which does not use a counter, and noted that when the patentee intended to claim a counter, it did so explicitly (e.g., in claims 12 and 18).

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 11-19 and 32 of the ’876 patent as unpatentable.